Hmm, I estimate that the gain of a common emitter output stage running 100W into 8 ohms, is about 1500X.
(Of course the numbers get worse as the junctions warm up above 27 degrees C!)
Math: Ic = 5 amps peak; gm = 192 siemens at 5 amps; gm*RL = 1538X
And I estimate that the open loop output impedance of a common emitter output stage at 5 amps collector current, assuming the output transistor's Early voltage is 200V (which is what I usually measure), is about 40 ohms.Math: Ic = 5 amps, VA = 200V, ro = 200/5 = 40
And I estimate that the open loop output impedance of Bob Cordell's Emitter Follower output stage in Figure 3.14, is about 0.083 ohms.Math: Rext = (0.33/8) and Rinternal = 1/gm = Rext at optimum bias. Then Zout = Rext + Rint = 0.0825 ohms
So I estimate that going from EF to CE increases the output impedance by ~ 485X and increases the gain by ~ 1538X. Very thought provoking. Thank you!(Of course the numbers get worse as the junctions warm up above 27 degrees C!)
You are assuming that output impedance depends on the Gm of the output devices. This is not really the case. Imagine a JLH output stage driven by an LTP and current mirror. All that determines output impedance in this case is the Hfe of the 3 output stage transistors, and the transimpedance of the input stage. The same is true for most amplifiers which do not lose significant gain to parasitic leakage from VAS to ground.
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I do recommend the Cherry article I referenced above in IEEE.
"Loop Gain, Input Impedance and Output Impedance of Feedback Amplifiers"
28 pp, a few partial derivatives and matrix equations, references, circuits and all.
Then we can probably both learn from a discussion of it, maybe in my "Common Emitter..." thread so as not to hijack Bob's.
But his basic conclusion is that it all cancels out and the closed loop output impedance is identical.
He has previously said "It also turns out - but is much more difficult harder to prove - that the stability of the feedback loop is the same".
Best wishes
David
Keantoken, that link doesn't work, can't deep link.
Found it.
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OK, fixed now, I had a 503 error, server maintenance or similar, not a direct link block as I initially believed.
Kind of a one-sided version of the Bryston.
Best wishes
David
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In general I would say oscillation under 30MHz should be strongly suspected to be related to the feedback loop. Adjusting lead compensation is often more useful. If lead compensation is too high it can also be a problem.
In my use of class-A Sziklai/CFP output stage the distortion measured is significantly lower (1/10) than a CE OPS.
Comments?
THx-RNMarsh
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I have to disagree with this. In a reasonably designed/compensated global loop, with designed ULGF below about 2 MHz, it is very unlikely that oscillation due to the global loop will occur above 10MHz.
Again, I am not talking about completely ineptly-designed global feedback loops. Also, bear in mind that a lead compensation capacitor across the feedback resistor can create HF havoc if not wisely and sparingly used. I generally like to avoid them.
Cheers,
Bob
CFP in Class A is reasonable, maybe not quite optimal but difference should be inaudible, the problems are in Class B+.
I did quite a few simulations of CFP in Class A, there were some subtleties that I don't yet understand.
As to your exact results, I would need to see the circuit.
Best wishes
David
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This was tested unbiased? with what protocol?
Statistical level of confidence was?
Best wishes
David
I swear on my 465B! Lets say you're getting oscillation at 20MHz. Your MOSFET has Cgd of say 200pF. This means you need an inductance of 317nH to cause that oscillation. So how do you get 317nH, 13 inches of inductance, across the G-D pins of the MOSFET? It's not in the layout. The truth is more complicated.
http://www.diyaudio.com/forums/soli...mp-200w8r-400w4r-post4788953.html#post4788953
PS. I tend to use ~20MHz+ ULGF.
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How do they misbehave?
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It was Great Guru Baxandall who pointed out to me that in many cases .. eg the JLH 1969 Class A amp ... CE & EF are the same once you have taken into account changes in gain etc. That applies to Zo too.
I prefer simple EF2 type output stages but for other reasons. eg Bob's thermal issues and also overload behaviour.
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For the thermal issues, set up your THD meter and oscillator & measure at 1W or less. Then without touching anything, increase the oscillator output to 1/3 full power for max dissipation in your amp. Good oscillators should allow you to do this with a switch and without twiddling pots or touching anything else.
When your amp is stinking hot. Switch back to the 1W or less position. If you have set things up correctly, you should be able to measure the low level THD within 2 seconds of turning down the oscillator.
On many CFP amps, the THD residual will show HUGE amounts of crossover for several seconds while the amp cools down.
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Hi Ric, haven't seen you post for a while
Can we discuss a few points in my Common Emitter thread >HERE< so as not to hijack Bob's?
Best wishes
David
Hi Chris,
Can you post a schematic of the output stage and let us know at what current you set the output transistor bias?
How does THD-20 at about 10 watts look as a function of output stage bias current?
Cheers,
Bob
Hi kean,
What is your 465B? A Tek scope?
I agree that things are complicated with HF parasitic oscillations in MOSFETs. The equivalent ft of vertical MOSFETs (gm/(Cgs+Cgd)) is very high, especially at higher current where gm is big. Bondwire and package inductances also play a role.
If you are compensating your amplifier to ULGF of 20 MHz or more, it is not surprising that you may be seeing global loop oscillations in the 10-50MHz range, but that does not fall into the assumption that I made in my earlier post that ULGF was below 2 MHz.
I certainly don't have the Brass to design my amplifiers for ULGF of 20MHz
.BTW, why are you running ULGF at 20+ MHz?
I think it is not unreasonable to find stray inductance combinations of, say, 10nH, here and there on the G, S an D pins. There are also capacitances that can be on the order of 1000pF or more within a MOSFET, be it Cgd, Cgs or Cds, depending on voltages. As a point of reference, I think 10nH and 1000pF resonates at about 50MHz.
There is also the opportunity for complex interactions with the driver transistor. A simple observation is that the output of an emitter follower is inductive, so this can go into the mix as well. And the impedance at the output of the EF driver depends the driver's input impedance, which is the output impedance of the VAS (which may be Miller compensated). The key to all of this is to what extent a SPICE simulation can reveal some of the parasitic oscillation tendencies given the limitations of the transistor models and modeling of the real-world parasitics.
An EF driver transistor with ft of 50MHz and 100 ohms resistive base circuit impedance will have an equivalent output inductance on the order of 300nH if I am not mistaken.
Cheers,
Bob