Amplifier Gain Calculations
Hi All,
I have gone through chapter 2 of bob's book a few times and manually written out
the process of calculating the IPS Gain, VAS Gain and OPS Gain.
I also now have a much better understanding of how to calculate the closed loop gain. error factor, loop gain etc thanks to chapter 4.
I am happy that I am now able to calculate out and understand the process involved in calculating the correct gains - for open and closed loop etc.
So I thought that I would go over the process once more in LTspice using the numbers from the DC analysis of the basic amplifier figure 2.2 that are shown in the
example file Amplifier DC.asc in the examples folder 'Figure 19_7' --> 'DC'
I ran the analysis and printed out the results for the DC operating points and the Spice error log for the transistor details.
After using those results to calculate the Gains for the IPS Gain, VAS Gain and OPS Gain.
I found that the IPS & OPS numbers matched quite closely to chapter 2 of the book
'IPS' Gain = 14.4 or 23.17DB
'OPS' Gain = 0.9655 or -0.304DB
However the numbers for the VAS Gain are way off and it looks like from my limited knowledge on the subject that the numbers for the Early effect 'Ro' have a large discrepancy.
The gain that I am getting for the VAS is 2747.8 or 68.779 DB
So my questions are.
Is the value for Ro: in the spice error log for the transistors equal to the 'Early effect'
or is this some other parameter?
Because the number I am getting in the spice error log for 'Ro:' is 69400 ohms
which is a lot larger that the value in the book which is 13500 ohms
I know that the 'early voltage' in the book was just an estimate but when I calculated the early voltage back from 69400 ohms I got 667 which I'm assuming is to high.
If someone could provide some clarity on this it would be greatly appreciated.
Hi All,
I have gone through chapter 2 of bob's book a few times and manually written out
the process of calculating the IPS Gain, VAS Gain and OPS Gain.
I also now have a much better understanding of how to calculate the closed loop gain. error factor, loop gain etc thanks to chapter 4.
I am happy that I am now able to calculate out and understand the process involved in calculating the correct gains - for open and closed loop etc.
So I thought that I would go over the process once more in LTspice using the numbers from the DC analysis of the basic amplifier figure 2.2 that are shown in the
example file Amplifier DC.asc in the examples folder 'Figure 19_7' --> 'DC'
I ran the analysis and printed out the results for the DC operating points and the Spice error log for the transistor details.
After using those results to calculate the Gains for the IPS Gain, VAS Gain and OPS Gain.
I found that the IPS & OPS numbers matched quite closely to chapter 2 of the book
'IPS' Gain = 14.4 or 23.17DB
'OPS' Gain = 0.9655 or -0.304DB
However the numbers for the VAS Gain are way off and it looks like from my limited knowledge on the subject that the numbers for the Early effect 'Ro' have a large discrepancy.
The gain that I am getting for the VAS is 2747.8 or 68.779 DB
So my questions are.
Is the value for Ro: in the spice error log for the transistors equal to the 'Early effect'
or is this some other parameter?
Because the number I am getting in the spice error log for 'Ro:' is 69400 ohms
which is a lot larger that the value in the book which is 13500 ohms
I know that the 'early voltage' in the book was just an estimate but when I calculated the early voltage back from 69400 ohms I got 667 which I'm assuming is to high.
If someone could provide some clarity on this it would be greatly appreciated.
Sometimes it helps me to simulate and plot the ICE versus VCE curves of a transistor model, at several different values of IBE.
In this case it might be a useful idea because the circuit designer could then extrapolate those I-V curves and find the actual, as-simulated, Early voltage with no ambiguity or confusion. Either by printing the curves on paper and using a ruler; or by applying the analysis methods we learned in algebra-2 as 17 year olds.
In this case it might be a useful idea because the circuit designer could then extrapolate those I-V curves and find the actual, as-simulated, Early voltage with no ambiguity or confusion. Either by printing the curves on paper and using a ruler; or by applying the analysis methods we learned in algebra-2 as 17 year olds.
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Hi Stuart,
The value Ro in the SPICE error log is the small-signal output impedance of the transistor at that DC operating point. It is not the Early effect, or the Early effect voltage, but it is governed by the Early effect and the Early effect parameter VA in the SPICE model.
Bear in mind that if you are using the cordell models, many of those models were generated AFTER the book was published. The sims in the book were based on, I believe, models that were in the LTspice library at the time. In other words, if you are using the cordell models to simulate circuits in the book, you may not get identical results to those stated in the book.
Cheers,
Bob
Hi Bob, Thank you for that input. I did not know that Ro in the ltspice log was small-signal output impedance. I'll review all that and what Mark said about and see how I go calculating the gain etc.
I'm just trying to understand how to calculate the gains based on the information that LTSpice. provides and using aLTSpice. model. (your example model in this case).
I understand that its not going to match the book exactly, but I am assuming that I should be able to calculate the gains using the process described in the book and the figures from LTSpice.
I'm just trying to understand how to calculate the gains based on the information that LTSpice. provides and using aLTSpice. model. (your example model in this case).
I understand that its not going to match the book exactly, but I am assuming that I should be able to calculate the gains using the process described in the book and the figures from LTSpice.
After reviewing what I had posted previously. I realized that I made a mistake
with the following question
[special=Is the value for Ro: in the spice error log for the transistors equal to the small-signal output impedance' or is this some other parameter?]%[/special]
A big thank you to bob for confirming it is the small-signal output impedance.
It was a big typo on my behalf. I apologize for not reviewing my post.
However I am sill unable to get the calculations to match.
Any help advising me were I am going wrong would be appreciated.
To calculate VAS open loop gain I have been using the following method.
from my interpenetration of Bob's book.
So using the numbers from LTSpice I get.
Name: q4
Model: 2n5551c
Gm: 3.60e-01
Ro: 6.85e+04
Name: q8
Model: mje243c
BetaDC: 1.46e+02
Name: q10
Model: mjl21194c
BetaDC: 4.06e+01
Aol vas = Zncl / Rvas
Rvas = 22 + 1/gm (Q4) = 24.778
Zncl = Rout // Zin Ops
Zin Ops = Beta x RL
Zin Ops = 146 (Q8) x 40.6 (Q10) x 8
Zin Ops = 47420.8
Rout = Ro(Q4) x degeneration factor
degeneration factor = (re' + RE) / re' or (1/gm (Q4) + RE) / 1/gm (Q4)
degeneration factor = 8.92
Rout = 68500 x 8.92
Rout = 68500 x 8.92
Rout = 611020
Zncl = Rout // Zin Ops
Zncl = 611020 // 47420.8
Zncl = 44005
Aol vas = Zncl / Rvas
Aol vas = 44005 / 24.778
Aol vas = 1776 or 65db
Now when I run an AC analysis on the open loop circuit I get.
A gain at the VAS of 84.03db - 21.14db (IPS) = 62.9db at 100Hz
62.9db or 1395
This is what I don't understand why are the calculation coming out differently
I have attached the relevant files if some one has the time to try and clear this up for me.
[special=One thought that I had that may explain the differences in Aol VAS is that one LTSpice analysis is done in DC with an offset voltage of 0.0023v while
the AC analysis is done a 1V. This would of course change the beta values of Q8 & Q10 and the gm value of Q4.]%[/special]
with the following question
The question should have read.
[special=Is the value for Ro: in the spice error log for the transistors equal to the small-signal output impedance' or is this some other parameter?]%[/special]
A big thank you to bob for confirming it is the small-signal output impedance.
It was a big typo on my behalf. I apologize for not reviewing my post.
However I am sill unable to get the calculations to match.
Any help advising me were I am going wrong would be appreciated.
To calculate VAS open loop gain I have been using the following method.
from my interpenetration of Bob's book.
So using the numbers from LTSpice I get.
Name: q4
Model: 2n5551c
Gm: 3.60e-01
Ro: 6.85e+04
Name: q8
Model: mje243c
BetaDC: 1.46e+02
Name: q10
Model: mjl21194c
BetaDC: 4.06e+01
Aol vas = Zncl / Rvas
Rvas = 22 + 1/gm (Q4) = 24.778
Zncl = Rout // Zin Ops
Zin Ops = Beta x RL
Zin Ops = 146 (Q8) x 40.6 (Q10) x 8
Zin Ops = 47420.8
Rout = Ro(Q4) x degeneration factor
degeneration factor = (re' + RE) / re' or (1/gm (Q4) + RE) / 1/gm (Q4)
degeneration factor = 8.92
Rout = 68500 x 8.92
Rout = 68500 x 8.92
Rout = 611020
Zncl = Rout // Zin Ops
Zncl = 611020 // 47420.8
Zncl = 44005
Aol vas = Zncl / Rvas
Aol vas = 44005 / 24.778
Aol vas = 1776 or 65db
Now when I run an AC analysis on the open loop circuit I get.
A gain at the VAS of 84.03db - 21.14db (IPS) = 62.9db at 100Hz
62.9db or 1395
This is what I don't understand why are the calculation coming out differently
I have attached the relevant files if some one has the time to try and clear this up for me.
[special=One thought that I had that may explain the differences in Aol VAS is that one LTSpice analysis is done in DC with an offset voltage of 0.0023v while
the AC analysis is done a 1V. This would of course change the beta values of Q8 & Q10 and the gm value of Q4.]%[/special]
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Power Amplifier Design Evolution
Hi All,
Over the weekend I read through chapter 3 of bob's book.
All I can say is wow, that was so awesome. So informative and really helped clarify
a lot of things for me. A big thank you to you Bob for going to all that effort to release such an awesome book.
To try and give a little back to the forum and other readers.
I make up a little excel spreadsheet so people can use it if they like for
Amplifier design comparison.
I hope that it helps others.
I also had a go at the creating Figure 3.3, which shows the
Differential stage current versus input voltage
There are two files there to look at if anyone interested.
Un-degenerated & Degenerated - Stepped from 1:1 to 10:1
Don't forget to load the plot settings.
Enjoy
Hi All,
Over the weekend I read through chapter 3 of bob's book.
All I can say is wow, that was so awesome. So informative and really helped clarify
a lot of things for me. A big thank you to you Bob for going to all that effort to release such an awesome book.
To try and give a little back to the forum and other readers.
I make up a little excel spreadsheet so people can use it if they like for
Amplifier design comparison.
I hope that it helps others.
I also had a go at the creating Figure 3.3, which shows the
Differential stage current versus input voltage
There are two files there to look at if anyone interested.
Un-degenerated & Degenerated - Stepped from 1:1 to 10:1
Don't forget to load the plot settings.
Enjoy
Last edited:
Great advice, Mooly thanks for that. I'll have a closer look.
I guess that when I saw the no load waveform I assumed that maybe the resistor value that I was using was incorrect.
I thought that it would be good if I could verify what value I should use. As I didn't see anything in bob's book stating how to simulate a non load circuit.
I am a newbie at this and thought that asking more experienced people here on the forum would be a good place to start.
Sent from my SM-G920I using Tapatalk
I guess that when I saw the no load waveform I assumed that maybe the resistor value that I was using was incorrect.
I thought that it would be good if I could verify what value I should use. As I didn't see anything in bob's book stating how to simulate a non load circuit.
I am a newbie at this and thought that asking more experienced people here on the forum would be a good place to start.
Sent from my SM-G920I using Tapatalk
Mooly is right, no load is just that, no load. I guess you sim no load to see what your circuit does, so what you see is what your circuit does without load ;-)
But to gain confidence, sim it with the regular load and then step up the load impedance towards no load and see what happens when you increase it. That may give you an insight where it starts to do things you would not expect.
Jan
But to gain confidence, sim it with the regular load and then step up the load impedance towards no load and see what happens when you increase it. That may give you an insight where it starts to do things you would not expect.
Jan
Hi Stuart,
A no-load condition should never create a problem for a conventional solid-state amplifier. In practice, a 100-ohm load should be sufficiently close to no load for most testing. However, the amp should behave properly with no load at all. I do it all the time.
Make certain that you have included the R-C Zobel shunt network to ground in a location not far from the output transistors. This provides a minimum load of usually on the order of 10 ohms at high frequencies, and is important to output stage stability.
Cheers,
Bob
Thanks for your input bob. I've just been working through and simulating the circuits as they are shown in chapter three. I have been able to run 1k and 20k THD simulations with great results which show improvements as noted in you're book.
2, 4, and 8 ohm simulations work well. I've had a problem running no load simulations. Probably due to my lack of understanding of how to simulate them correctly.
I do not have a Zobel shunt network attached. And to be honest I don't really know what that is.
I understand that I need to add a components to the input and output (when I complete the circuit) as shown in your book. Section 3.11 completing the amplifier.
I'll review section 3.11 again and see how I go. However I thought I needed to simulated the circuits dc coupled.
Thanks again.
Sent from my SM-G920I using Tapatalk
2, 4, and 8 ohm simulations work well. I've had a problem running no load simulations. Probably due to my lack of understanding of how to simulate them correctly.
I do not have a Zobel shunt network attached. And to be honest I don't really know what that is.
I understand that I need to add a components to the input and output (when I complete the circuit) as shown in your book. Section 3.11 completing the amplifier.
I'll review section 3.11 again and see how I go. However I thought I needed to simulated the circuits dc coupled.
Thanks again.
Sent from my SM-G920I using Tapatalk