I once and only once, burnt out a base stopper.
I don't know what caused that, but it was a 1r0 600mW through hole metal film.
It may have been oscillation when testing my Krell Klone into 100nF output cap.
I did not at that time consider making my base stoppers bigger. Their blowing may be why none of my output devices were damaged. It was a 6pair output stage which could pass >30Apk for medium term transients and possibly >100Apk for short term transients.
I don't know what caused that, but it was a 1r0 600mW through hole metal film.
It may have been oscillation when testing my Krell Klone into 100nF output cap.
I did not at that time consider making my base stoppers bigger. Their blowing may be why none of my output devices were damaged. It was a 6pair output stage which could pass >30Apk for medium term transients and possibly >100Apk for short term transients.
Well, you do need to take account of the possibility of high current transients, which when averaged out do not take the resistor above its power dissipation limit, but nonetheless will break the device.
You can get pulse-rated surface-mount resistors, for not much more $ than “normal” ones. Modern switch-mode circuits employ surface-mount resistors (sometimes as small as 0603 or 0402 imperial) in the gate-drive path of the power switches. During the turn-on and turn-off transients of the power devices, these resistors pass high current pulses which can easily blow “standard” resistors, even if, on average, their power dissipation is well below the rated level. Pulse-rated resistors work fine in this situation.
Finally, a voice of sanity. Five lines saying exactly what I was trying to convey for the last several days.
You are reading into
Average levels are one limitation.
Transient overload levels are a different limitation.
But in BOTH average and transient it is power dissipation that sets the limits.
He also tells us
We all know that transients can pass safely through devices.
very long transients can usually only be slightly higher than the average levels. Very short transients can be of higher levels and in some cases very much higher levels. Two examples that show the very high level tolerance to transients are fuses and transistors. The manufacturers give us data on how much overload they can tolerate.
We were recently discussing melf type resistors. This is another where the manufacturer gives us overload tolerance data.
Oh, and I can't forget transformers. They can tolerate enormous transient overloads. Try momentarily shorting the secondary while powered by the mains. The transient current peak could well be 1000 times the rated secondary current. But the insulation does not get damaged if the power dissipation does not raise the temperature of the insulation above it's rated temperature.
But in all cases we are referring to the components tolerance to power dissipation, basically: I²R
more than he has actually told us.
Average levels are one limitation.
Transient overload levels are a different limitation.
But in BOTH average and transient it is power dissipation that sets the limits.
He also tells us
again he is differentiating between average levels and transient overloads.
We all know that transients can pass safely through devices.
very long transients can usually only be slightly higher than the average levels. Very short transients can be of higher levels and in some cases very much higher levels. Two examples that show the very high level tolerance to transients are fuses and transistors. The manufacturers give us data on how much overload they can tolerate.
We were recently discussing melf type resistors. This is another where the manufacturer gives us overload tolerance data.
Oh, and I can't forget transformers. They can tolerate enormous transient overloads. Try momentarily shorting the secondary while powered by the mains. The transient current peak could well be 1000 times the rated secondary current. But the insulation does not get damaged if the power dissipation does not raise the temperature of the insulation above it's rated temperature.
But in all cases we are referring to the components tolerance to power dissipation, basically: I²R
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The confusion arrises from that simple phrase “power dissipation”!
Let’s be rigorous about this and that should end the confusion/“disagreement”:
Usually, the phrase “power dissipation” is taken to mean “power dissipation averaged over an amount of time”, this amount of time usually being one or more complete periods of some signal or other - in the case of an audio amplifier, perhaps over a complete period of a sinusoidal input/output signal, in a switch-mode circuit perhaps over a switching period, etc. etc.
For a two-terminal component, instantaneous power transfer to that component is given by the product of voltage across the terminals and current flowing through the terminals. For a dissipative component such as a resistor, the vast majority of this instantaneous power is dissipated as heat (some is stored in the parasitic reactive elements (inductance and capacitance)).
If voltage and current vary as functions of time, i.e. voltage = V(t) and current = I(t), then the instantaneous power is given by P(t)=V(t)*I(t). If P(t) never exceeds the rated power, then your component isn’t going to fail.
However, usually we average P(t) over time: P(av) = (1/T) * (<integral from 0 to T>P(t)dt). Here, it’s possible that P(av) is below the rated power, but that at some point from t=0 to t=T, P(t) exceeded the rated power. Whether this momentary excursion above rated power will damage the device or not depends upon the duration of the event, the amount by which the rated power was exceeded, and the device’s transient overload capability.
I believe that Waly was mainly trying to point out that the transient overload of “standard” surface-mount resistors is low, relative to through-hole counterparts. I also believe, as Andrew points out, that MELF surface-mount resistors are constructed similarly to through-hole resistors so should fare better in this regard. Other surface-mount resistors with “superior” transient overload capability are available.
Hopefully we all agree now and can move on!
Let’s be rigorous about this and that should end the confusion/“disagreement”:
Usually, the phrase “power dissipation” is taken to mean “power dissipation averaged over an amount of time”, this amount of time usually being one or more complete periods of some signal or other - in the case of an audio amplifier, perhaps over a complete period of a sinusoidal input/output signal, in a switch-mode circuit perhaps over a switching period, etc. etc.
For a two-terminal component, instantaneous power transfer to that component is given by the product of voltage across the terminals and current flowing through the terminals. For a dissipative component such as a resistor, the vast majority of this instantaneous power is dissipated as heat (some is stored in the parasitic reactive elements (inductance and capacitance)).
If voltage and current vary as functions of time, i.e. voltage = V(t) and current = I(t), then the instantaneous power is given by P(t)=V(t)*I(t). If P(t) never exceeds the rated power, then your component isn’t going to fail.
However, usually we average P(t) over time: P(av) = (1/T) * (<integral from 0 to T>P(t)dt). Here, it’s possible that P(av) is below the rated power, but that at some point from t=0 to t=T, P(t) exceeded the rated power. Whether this momentary excursion above rated power will damage the device or not depends upon the duration of the event, the amount by which the rated power was exceeded, and the device’s transient overload capability.
I believe that Waly was mainly trying to point out that the transient overload of “standard” surface-mount resistors is low, relative to through-hole counterparts. I also believe, as Andrew points out, that MELF surface-mount resistors are constructed similarly to through-hole resistors so should fare better in this regard. Other surface-mount resistors with “superior” transient overload capability are available.
Hopefully we all agree now and can move on!
Its a shame you failed so miserably.
Seriously, give us a break. You got it wrong at the beginning and failed to extract yourself with your semantic back-peddling.
Cheers,
Bob
Hi Bob, Hi All,
This is my first post on this forum.
I have a Question in relation to your book.
On page 44 you mention how the early effect of Q4 affects the collector load. A value of 35V is assigned to Vce of Q4. I am just wondering if you could help explain were the value of 35V came from as I modeled the circuit in everycircuit and it comes up with a value of 57.6V if I measure directly across Vce of Q4.
From the text its not clear what that bias condition or input voltage of the circuit is. I guess if the input voltage is at 0. This creates a Vce of about 35v. So everything then makes scenes.
I also did notice last night when re-reading page 20 were the topic of early effect was first introduced that about half way down the page.
[book="A 2N5551 VAS transistor biased at 10 mA and having no emitter degeneration will
have an output resistance on the order of 14 kΩ at a collector-emitter voltage of 35 V.
This would correspond to a signal output voltage of 0 V in an arrangement with ± 35 V
power supplies. "]%[/book]
So I probably just answered my own
This is my first post on this forum.
I have a Question in relation to your book.
On page 44 you mention how the early effect of Q4 affects the collector load. A value of 35V is assigned to Vce of Q4. I am just wondering if you could help explain were the value of 35V came from as I modeled the circuit in everycircuit and it comes up with a value of 57.6V if I measure directly across Vce of Q4.
From the text its not clear what that bias condition or input voltage of the circuit is. I guess if the input voltage is at 0. This creates a Vce of about 35v. So everything then makes scenes.
I also did notice last night when re-reading page 20 were the topic of early effect was first introduced that about half way down the page.
[book="A 2N5551 VAS transistor biased at 10 mA and having no emitter degeneration will
have an output resistance on the order of 14 kΩ at a collector-emitter voltage of 35 V.
This would correspond to a signal output voltage of 0 V in an arrangement with ± 35 V
power supplies. "]%[/book]
So I probably just answered my own
Just wondering if anyone can provide some extra clarity on the following
Page 45 of Bob's book.
[book=If the amplifier is producing 20 V at its output, the error signal across the bases of Q1 and Q2 needs only to be 20/16,300 = 1.2 mV. Earlier it was asserted that the closed- loop gain would be approximately 20 on the basis of the feedback network attenuating the output by a factor of 20 and the required differential input to the amplifier being small. Because the input only needs to be 1.2 mV (compared to the input signal level of 1 V), it is apparent that this is a very good approximation.]%[/book]
Q1. Is the number 20 in the following 20/16,300 = 1.2 mV.
the 20v output voltage or is it the closed- loop gain.
Q2. When I set the input voltage to 1V (base of Q1) the attenuated the output voltage (base of Q2) is 1.02V. Is this correct? I would have thought that the input voltage would have to be 1.0012V (base of Q1) to get an
attenuated output voltage at the base of Q2 to be 1.0V if the output is 20V.
Really not sure on this one and help providing some extra clarity would be very much appreciated.
Page 45 of Bob's book.
[book=If the amplifier is producing 20 V at its output, the error signal across the bases of Q1 and Q2 needs only to be 20/16,300 = 1.2 mV. Earlier it was asserted that the closed- loop gain would be approximately 20 on the basis of the feedback network attenuating the output by a factor of 20 and the required differential input to the amplifier being small. Because the input only needs to be 1.2 mV (compared to the input signal level of 1 V), it is apparent that this is a very good approximation.]%[/book]
Q1. Is the number 20 in the following 20/16,300 = 1.2 mV.
the 20v output voltage or is it the closed- loop gain.
Q2. When I set the input voltage to 1V (base of Q1) the attenuated the output voltage (base of Q2) is 1.02V. Is this correct? I would have thought that the input voltage would have to be 1.0012V (base of Q1) to get an
attenuated output voltage at the base of Q2 to be 1.0V if the output is 20V.
Really not sure on this one and help providing some extra clarity would be very much appreciated.
Hi!
Do you think it is generally true, but on the base of Q1 will be 1000 mV by the condition of the sample, and on the basis of Q2 - 998,8 mV.
16300 gain is the open loop gain which by calculation is ~+84dB
20Vac is the output.
An opamp with feedback tries to make the output such that the TWO inputs become equal. The error in this inequality is the output voltage divided by the open loop gain. i.e. at an output voltage of 20Vac the differential input voltage will be 20Vac/16300 = 1.2mVac
The actual voltage at the inputs will be output voltage divided by closed loop gain.
The diff you measured 1V:1.02V seems to be an experimental error.
It should show 1.0000Vac:1.0012Vac but you would probably need a 200000 count DMM to read that with any confidence. A 2000count DMM has no hope of reading those two voltages accurately enough. A 50000 count DMM might just about read that but I would not have much confidence in the experimental result, especially in view of interference corrupting that result.
20Vac is the output.
An opamp with feedback tries to make the output such that the TWO inputs become equal. The error in this inequality is the output voltage divided by the open loop gain. i.e. at an output voltage of 20Vac the differential input voltage will be 20Vac/16300 = 1.2mVac
The actual voltage at the inputs will be output voltage divided by closed loop gain.
The diff you measured 1V:1.02V seems to be an experimental error.
It should show 1.0000Vac:1.0012Vac but you would probably need a 200000 count DMM to read that with any confidence. A 2000count DMM has no hope of reading those two voltages accurately enough. A 50000 count DMM might just about read that but I would not have much confidence in the experimental result, especially in view of interference corrupting that result.
Thanks for the input and explanations.
So, just to confirm the base of Q1 should be 1.0012v and the base of Q2 should be 1.00v
The Closed loop gain will be Output voltage of 20vac / 1.0012 which is ~19.97
This is what I thought based on bob's book however the simulation I ran gave me unexpected results. Which is when things became unclear.
Sent from my SM-G920I using Tapatalk
So, just to confirm the base of Q1 should be 1.0012v and the base of Q2 should be 1.00v
The Closed loop gain will be Output voltage of 20vac / 1.0012 which is ~19.97
This is what I thought based on bob's book however the simulation I ran gave me unexpected results. Which is when things became unclear.
Sent from my SM-G920I using Tapatalk
I just modelled the circuit in figure 2.12 using everycircuit. The results were that if the input was 1v at the base of Q1 the voltage at base of Q2 was 1.02v.
If I set the input at the base of Q1 to 1.0012v as per my manual calculations based on the open loop gain. I get 1.0239v at the base of Q2 which made on sence. To get the correct results I had to change the value of R1 to 1.41K
I will model the circuit in LTSpice over the weekend and see how I go.
Thanks for your interest.
Sent from my SM-G920I using Tapatalk
Hi Bob, Hi All,
This is my first post on this forum.
I have a Question in relation to your book.
On page 44 you mention how the early effect of Q4 affects the collector load. A value of 35V is assigned to Vce of Q4. I am just wondering if you could help explain were the value of 35V came from as I modeled the circuit in everycircuit and it comes up with a value of 57.6V if I measure directly across Vce of Q4.
From the text its not clear what that bias condition or input voltage of the circuit is. I guess if the input voltage is at 0. This creates a Vce of about 35v. So everything then makes scenes.
I also did notice last night when re-reading page 20 were the topic of early effect was first introduced that about half way down the page.
[book="A 2N5551 VAS transistor biased at 10 mA and having no emitter degeneration will
have an output resistance on the order of 14 kΩ at a collector-emitter voltage of 35 V.
This would correspond to a signal output voltage of 0 V in an arrangement with ± 35 V
power supplies. "]%[/book]
So I probably just answered my own
Hi Stuart,
Welcome to posting on the forum and thank you for bringing to light an area in the book where I could have been more clear just with the addition of one phrase or sentence. I apologize for the confusion. Yes, on page 44 I was referring to the amplifier example where the rails were 35V and the quiescent condition was with approximately 0V at the output, placing approximately 35V across the transistor. In reality the number is a bit smaller due to the drop on the bias spreader and the drop on the emitter resistor of the VAS.
These are the kinds of feedback that help me improve the second edition.
Cheers,
Bob
Hi Stuart,
Q1: in this case the 20 refers to the output voltage, but it is also true that the CLG is very close to 20.
Q2: The attenuated output voltage would be 1.000V if the output voltage was exactly 20V, but the attenuated output voltage is ever so slightly less than that because the CLG is slightly less than 20. The attenuated output voltage will actually be 1.000V less 1.2mV, leaving 1.2mV to drive the input stage when the input voltage on the other side is 1.0V.
Cheers,
Bob
Hi Stuart,
If the input to the amplifier presented to Q1 is 1.000V, the signal presented to the base of Q2 should be smaller by 1.2mV, not larger.
Cheers,
Bob
This shows that the OL gain from your sim circuit is less than 16300. Depending on your models, it can vary all over the place.
In fact, that is the main reason to use feedback: to make sure that even when the OL gain varies 20% between units, the CL gain only varies a fraction of a % or so.
Your CL gain should be very close to 20 anyway; is it?
Jan