Agree - that's what I have been working on recently on the recently neglected (by me) thread. Looks promising I think.
Cascoded R100 Circlotron with minimal 3rd harmonic
Here is an idea for a Circlotron optimized for a low 3rd harmonic by eliminating the source degeneration resistors and cascoding the output FETs. Both mathematical analysis and simulation results indicate that by minimizing the source resistance (both internal to the FET and external) and eliminating the Early effect via cascoding the 3rd (and higher) harmonic is minimized.
Because bias stability vs. temperature will be an issue with the elimination of the source resistors, this version of the design uses SemiSouth SJEPR100 FETs. Since the Vgs of the R100s is so low, optional current sources are used to increase the voltage gain of the JFET input stages, allowing the JFET load resistors to have higher values.
Shown below are the schematic and simulation harmonic distortion results vs. frequency and Watts. I have not built this yet.
Here is an idea for a Circlotron optimized for a low 3rd harmonic by eliminating the source degeneration resistors and cascoding the output FETs. Both mathematical analysis and simulation results indicate that by minimizing the source resistance (both internal to the FET and external) and eliminating the Early effect via cascoding the 3rd (and higher) harmonic is minimized.
Because bias stability vs. temperature will be an issue with the elimination of the source resistors, this version of the design uses SemiSouth SJEPR100 FETs. Since the Vgs of the R100s is so low, optional current sources are used to increase the voltage gain of the JFET input stages, allowing the JFET load resistors to have higher values.
Shown below are the schematic and simulation harmonic distortion results vs. frequency and Watts. I have not built this yet.
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BTW: I have done a similar design for the balanced F5, eliminating the source resistors and cascoding the output FETs. However, I have not studied the bias-current vs. temperature issues. It might be possible to use VDMOS FETs with appropriate thermistors, probably near the cascode FETs since they dissipate most of the power.
Here is the promised balanced-F5 with cascoding and no output degeneration. The simulation includes thermistors for control of bias current vs. temperature.
The harmonic spectrum looks too good to advertise yet. Simply incredible. I am not sure I believe some of the Spice model parameters for the FQA28N15 and FQA36P15 MOSFETs, particularly the internal source resistance Rs.
The next step is to see if I can modify one of my space F5TBS V1.1 boards to test this design, or generate a new PCB layout and order boards.
The harmonic spectrum looks too good to advertise yet. Simply incredible. I am not sure I believe some of the Spice model parameters for the FQA28N15 and FQA36P15 MOSFETs, particularly the internal source resistance Rs.
The next step is to see if I can modify one of my space F5TBS V1.1 boards to test this design, or generate a new PCB layout and order boards.
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Thanks Buzz.
BTW: If the thermistor based bias current control doesn't work, I have a fallback using a current servo.
Here is a schematic of the servo I simulated in my Cascoded Circlotron, it looks very good, but too many parts. There is probably a IC part that combines a voltage reference and opamp. The main problem is that the voltages being sensed are near the rails of the opamp, thus the need for the Zener diodes to offset the voltages.
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Finally someone took the bait!
Source degeneration and cascoding are largely independent design choices, but in combination they help minimize output stage generated harmonics.
If you analyze the MOSFET equation for drain current vs. gate voltage, you find that two parameters contribute to 3rd order and higher harmonics: the internal and external source degeneration resistance Rs, and the Lambda parameter "Early Effect".
- Eliminating the external source resistors greatly reduces the higher order harmonics due to the local feedback in the output stage.
- Choose MOSFETs with low Rs.
- Cascoding eliminates the contribution due to the Early Effect.
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Cascoding doesn't seem to have much effect on stability (except that the simulations sometimes complain).
Source resistance definitely affects stability, thus the concerns over thermistor based bias control, with a fallback to a current servo.
I had read abut Rs and high order distortion. Mosfets with low Rs are hard to find, correct. Early effect i hpave heard, but mostly in bjt circles.Finally someone took the bait!
Source degeneration and cascoding are largely independent design choices, but in combination they help minimize output stage generated harmonics.
If you analyze the MOSFET equation for drain current vs. gate voltage, you find that two parameters contribute to 3rd order and higher harmonics: the internal and external source degeneration resistance Rs, and the Lambda parameter "Early Effect".
- Eliminating the external source resistors greatly reduces the higher order harmonics due to the local feedback in the output stage.
- Choose MOSFETs with low Rs.
- Cascoding eliminates the contribution due to the Early Effect.
Somebody has to be the fish.
I would imagine a servo is in you future.
Still impressed. Pass has patent on cascode output. Have you looked at it?
Yes, and then the nonlinear contributions due the the Early Effect are gone, leaving only the Rs part in the equation. Here are the equations, where Vov = Vgs - Vth, the gate voltage about the threshold voltage:
The full equation:
Id = Kp/2 * (Vov - Id*Rs) * (1 + Lamba * (Vds - Id*(Rd + Rs)))
After cascoding:
Id = Kp/2 * (Vov - Id*Rs)
The image below show the nonlinear solution for the drain current Id and its Taylor series expansion, whose coefficients correspond to the harmonics generated. By reducing Rs (for a given Kp and Vov), the higher order harmonics are thus reduced.
There are other major advantages to cascoding the output stage:
Eagerly await my next post?
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Since you are biting your nails for the next episode:
Cascoding the output stage allows for very high output from only a single modulating FET on each rail without power dissipation problems. This also means that each driver stage is only driving the capacitance of a single FET.
Multiple cascode FETs are paralleled, with small source resistors to minimize current hogging. Most of the power is dissipated here.
Cascoding the output stage allows for very high output from only a single modulating FET on each rail without power dissipation problems. This also means that each driver stage is only driving the capacitance of a single FET.
Multiple cascode FETs are paralleled, with small source resistors to minimize current hogging. Most of the power is dissipated here.
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Thus far, only simulations which show THD at 1 watt below 0.001% 1kHz to 20kHz, and 40 1kHz, watt THD below 0.001%. These numbers are too good to be totally believable. I suspect that the Spice model Rs values for the MOSFETs are too small.
Until I actually build this circuit I will not really know for sure. There are lots of component variations that will reduce the even order harmonic cancellation.
Train just bunched up on me. Could you explain further. What do you mean, high output?
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