Hi Jaka and John,
- The numbering is not correct, will be reordered.
- C308 should be 100nF, of course.
- HIP210x: HI/LI to be driven with inverted signals:
Okay, that's easy to change and more straightforward. The initial design should function too, because the HS input is connected to the HO driven Mosfet's source as usual. The lower Mosfets of this half bridge switches inversely also. My intention was, to let the internal bridges of the driver switch simultaneous, maybe it is a mischief.
- C306/307 (noise supression) of the first comparators are separated, C308 (second comparator stages) will be separated.
- Buffers: after performing a primitive simulation with FMMT617/717 I also believe, that the Emitter follower stage may speed up the gate drive. Especially the edges got a bit steeper. Before that I was not sure to get some additional tr/tf and tpd-mismatch, more than in the comparator stage.
Does anybody may suggest better comparators without built-in hysteresis, faster transition times, lower delay times, low bias current, but working from a 3V supply and with RRIOs?
Many thanks again for your hints.
Regards, Timo
- The numbering is not correct, will be reordered.
- C308 should be 100nF, of course.
- HIP210x: HI/LI to be driven with inverted signals:
Okay, that's easy to change and more straightforward. The initial design should function too, because the HS input is connected to the HO driven Mosfet's source as usual. The lower Mosfets of this half bridge switches inversely also. My intention was, to let the internal bridges of the driver switch simultaneous, maybe it is a mischief.
- C306/307 (noise supression) of the first comparators are separated, C308 (second comparator stages) will be separated.
- Buffers: after performing a primitive simulation with FMMT617/717 I also believe, that the Emitter follower stage may speed up the gate drive. Especially the edges got a bit steeper. Before that I was not sure to get some additional tr/tf and tpd-mismatch, more than in the comparator stage.
Does anybody may suggest better comparators without built-in hysteresis, faster transition times, lower delay times, low bias current, but working from a 3V supply and with RRIOs?
Many thanks again for your hints.
Regards, Timo
Hi Timo,
look at datasheet for LT1711. But I do not think it would be a good idea to run comparators from 3V supply. I would go for triangle ramp amplitude as large as possible. Otherwise I am afraid you will find your circuit (or any other similar) susceptible to output stage transients when operating with very small input signals (duty cycle around 50%). This is the very reason I am trying to go with digital modulator now.
Best regards,
Jaka Racman
look at datasheet for LT1711. But I do not think it would be a good idea to run comparators from 3V supply. I would go for triangle ramp amplitude as large as possible. Otherwise I am afraid you will find your circuit (or any other similar) susceptible to output stage transients when operating with very small input signals (duty cycle around 50%). This is the very reason I am trying to go with digital modulator now.
Best regards,
Jaka Racman
Modulator type
Hi Jaka,
thank you for the help.
In my University project I use a µC (MSP430) with a 3.6V supply. Because of the simpler interfaces between the analogue and digital part I will use this supply for the analogue part also.
In a post you mentioned the notes of John Vanderkooy: Class D-2-25-03.pdf. This is a nice summary for several main issues of the Class D projects.
It shows a modulator type called 1st order entrained on page 7 (pdf's 6th). This seems to be synchronised by an external clock, isn't it? A simple synchronised (to the µc clock) modulator would be very interesting for the aforesaid project.
I tried to simulate it with LTSpice with various values of the feedback elements Ri, Rb, C and Rf, but I did not get it stable with only one frequency. The main behaviour was similar to the hysteretic modulator: the greater the modulation factor, the lower the frequency will be. The difference is, that the 1st order entrained modulator lowers its frequency by pulse skipping.
Does anybody know a functioning approach for this solution?
The other thing is, I could not find a possibility to integrate "external" spice models into a (e.g.) opamp or comparator. I also did not find the solution inside the help files. So the improvisational comparator is ugly.
Best regards, Timo
Hi Jaka,
thank you for the help.
In my University project I use a µC (MSP430) with a 3.6V supply. Because of the simpler interfaces between the analogue and digital part I will use this supply for the analogue part also.
In a post you mentioned the notes of John Vanderkooy: Class D-2-25-03.pdf. This is a nice summary for several main issues of the Class D projects.
It shows a modulator type called 1st order entrained on page 7 (pdf's 6th). This seems to be synchronised by an external clock, isn't it? A simple synchronised (to the µc clock) modulator would be very interesting for the aforesaid project.
I tried to simulate it with LTSpice with various values of the feedback elements Ri, Rb, C and Rf, but I did not get it stable with only one frequency. The main behaviour was similar to the hysteretic modulator: the greater the modulation factor, the lower the frequency will be. The difference is, that the 1st order entrained modulator lowers its frequency by pulse skipping.
Does anybody know a functioning approach for this solution?
The other thing is, I could not find a possibility to integrate "external" spice models into a (e.g.) opamp or comparator. I also did not find the solution inside the help files. So the improvisational comparator is ugly.
Best regards, Timo
Hi Timo,
This "entrained" modulator is a fairly common extension of self oscillating modulator. Basically it enables synchronization, but the price you have to pay is reduced power supply rejection ratio, which is very high in self oscillating design.
Simulation approach: First make working self oscillating design without Rb, then decrease Rb until you have synchronisation also at maximum input signal amplitude. Rb must always be larger than Ri assuming equal input signal and clock amplitude.
Best regards,
Jaka Racman
This "entrained" modulator is a fairly common extension of self oscillating modulator. Basically it enables synchronization, but the price you have to pay is reduced power supply rejection ratio, which is very high in self oscillating design.
Simulation approach: First make working self oscillating design without Rb, then decrease Rb until you have synchronisation also at maximum input signal amplitude. Rb must always be larger than Ri assuming equal input signal and clock amplitude.
Best regards,
Jaka Racman
Hi!
Do you know about a SHOP, where the EPCOS B64290-L699-X87 ferrite core is obtainable? This is the R63/38/25 toroid core from N87 material. Or any of Magnetics' KoolMu or APT FETs and SiC diodes? It is impossible in my country (just in pack quantities e.g. 192 pieces of that EPCOS toroid: 2 year wages .
)
Thanks,
Gyula
Do you know about a SHOP, where the EPCOS B64290-L699-X87 ferrite core is obtainable? This is the R63/38/25 toroid core from N87 material. Or any of Magnetics' KoolMu or APT FETs and SiC diodes? It is impossible in my country (just in pack quantities e.g. 192 pieces of that EPCOS toroid: 2 year wages .
)Thanks,
Gyula
Gyula said:Hi!
Do you know about a SHOP, where the EPCOS B64290-L699-X87 ferrite core is obtainable? This is the R63/38/25 toroid core from N87 material. Or any of Magnetics' KoolMu or APT FETs and SiC diodes? It is impossible in my country (just in pack quantities e.g. 192 pieces of that EPCOS toroid: 2 year wages .
Thanks,
Gyula
Ask for samples - you probably still have to pay full price. It worked in Norway.
Petter
Hi Petter!
Yes, but I haven't found sample order link at epcos www.epcos.com. There are a Product inquiry/sample ordering link but I think it is for price calculation.
Thank you!
Gyula
Yes, but I haven't found sample order link at epcos www.epcos.com. There are a Product inquiry/sample ordering link but I think it is for price calculation.
Thank you!
Gyula
Hi!
I saw two strange things in the TI PCM1798 datasheet:
1. Texas suggests the PLL1700 PLL based clock generator as a system clock (for optimal performance). The PCM1798 is capable of 123 dB SNR. Choosing a better one of PLL1707, the clock has approximately 50 ps RMS phase noise. The period time is 40 ns at 24.576 MHz, so the clock has 1.25% = 1250 ppm dither (or phase jitter). The 1.25% is not -123 dB.
Yesterday I just found a good clock at ILSI: I103-3N3-24.576 and at C-MAC: 24.576 CFPT-6133 AS and 24.576 CFPT-6144 AS.
2. The DAC hasn't got Vcom output for the I/V stage, the op.amps are grounded.
I think the PCM1798 will never be able to provide 0V output because the negative output current. The DAC has to got any kind of internal transistor at the output, so what will be with the op. amps' input offset voltage? I don't understand.
Gyula
I saw two strange things in the TI PCM1798 datasheet:
1. Texas suggests the PLL1700 PLL based clock generator as a system clock (for optimal performance). The PCM1798 is capable of 123 dB SNR. Choosing a better one of PLL1707, the clock has approximately 50 ps RMS phase noise. The period time is 40 ns at 24.576 MHz, so the clock has 1.25% = 1250 ppm dither (or phase jitter). The 1.25% is not -123 dB.
Yesterday I just found a good clock at ILSI: I103-3N3-24.576 and at C-MAC: 24.576 CFPT-6133 AS and 24.576 CFPT-6144 AS.
2. The DAC hasn't got Vcom output for the I/V stage, the op.amps are grounded.
I think the PCM1798 will never be able to provide 0V output because the negative output current. The DAC has to got any kind of internal transistor at the output, so what will be with the op. amps' input offset voltage? I don't understand.Gyula
SiC, BCA-design
Hello Gyula,
good to hear from you.
For the Infineon SiC-Diodes try:
EURODIS ENATECHNIK Electronics GmbH
Pascalkehre 1
25451 Quickborn
Germany
Phone: +49-4106-7 01 - 0
Fax: +49-4106-7 01 - 2 68
http://www.eurodis.com
or:
Rutronik Elektronische Bauelemente GmbH
Industriestraße 2
75228 Ispringen
Germany
Phone: +49-7231-80 10
Fax: +49-7231-8 22 82
http://www.rutronik.com
I bought 10 pieces of the SDB20S30 (2x10A, 300V) some weeks ago from there, but they do not have the whole range.
The EPCOS materials should be available at:
Spoerle Electronic
Váci út 45, 1134 Budapest
Tel 3506275/76, 3294202
Fax 3506277
(This address is already 3 years old.)
If you need the SiC and cannot purchase them, let me know, we will try to arrange something.
Additionally, I have some understanding problems with the BCA-design or better, with the minimisation of the deadtime in the output stage. As shown in the attached LTSpice-simulation, the main problem of the overlapping Vds and Id at each Mosfet still occurs.
Am I right, that this phenomenon prevents the possibility of zero deadtime between two alternately switched Mosfets in a half bridge configuration?
With increasing values of L2 + L3 (or L1, alternatively) arise heavy circulating currents through the inductors and the diodes. The power loss will be incredible.
What did I do wrong?
Best regards, Timo
Hello Gyula,
good to hear from you.
For the Infineon SiC-Diodes try:
EURODIS ENATECHNIK Electronics GmbH
Pascalkehre 1
25451 Quickborn
Germany
Phone: +49-4106-7 01 - 0
Fax: +49-4106-7 01 - 2 68
http://www.eurodis.com
or:
Rutronik Elektronische Bauelemente GmbH
Industriestraße 2
75228 Ispringen
Germany
Phone: +49-7231-80 10
Fax: +49-7231-8 22 82
http://www.rutronik.com
I bought 10 pieces of the SDB20S30 (2x10A, 300V) some weeks ago from there, but they do not have the whole range.
The EPCOS materials should be available at:
Spoerle Electronic
Váci út 45, 1134 Budapest
Tel 3506275/76, 3294202
Fax 3506277
(This address is already 3 years old.)
If you need the SiC and cannot purchase them, let me know, we will try to arrange something.
Additionally, I have some understanding problems with the BCA-design or better, with the minimisation of the deadtime in the output stage. As shown in the attached LTSpice-simulation, the main problem of the overlapping Vds and Id at each Mosfet still occurs.
Am I right, that this phenomenon prevents the possibility of zero deadtime between two alternately switched Mosfets in a half bridge configuration?
With increasing values of L2 + L3 (or L1, alternatively) arise heavy circulating currents through the inductors and the diodes. The power loss will be incredible.
What did I do wrong?
Best regards, Timo
Hello Timo!
Thank you for yor help about the shops, I will inquire which components are obtainable. I looked out the APT30SC60B for the PFC, and found good IGBTs at fairchild for the PSU and the PFC like the FGH50N6S2D. The hard switched topology can be made easily with the UCC3818 and the SiC. And it can be fast switched like a mud because of the nonexistent charge storing effect at the N-P boundary (the N-P boundary is nonexistent in the schottky )
I can't try the simulation because I haven't got Spice simulator, I should to download one. BUT I try to find the cause of fault on the way it works.. On behalf of understanding it's necessary to be familiar with the operation of inductances. I write the formulas in SI. One formula is enough for the BCA: dIdt=U/L where d means derive. So the rate of change of the current flowing across the inductance is equal to the quotient of Voltage switched to it and the value of inductivity. Switching an inductance parallel to a voltage generator the current flowing across the inductance is rising at the rate of change: U/L. Here the U is positive. With the removal of the Voltage gen., the current willn't be disappeared, just the direction of it's change will be opposite: the current will be falling. The inductance's voltage polarity will also be opposite, for it's attitude there is an another formula for the coil's voltage: U=n*dFidt where Fi is the magnetic flux. Fi=B*A, so Fi=(mo*mr*I*n)/l where mo: perbeability of air, mr: permeability of the material, I: the current flowing in the coil, n: number of turns of the coil, l: the magnetic path length. In normal condition the current can be changed, so it causes the change of magnetic flux (Fi). In this way dFidt is proportional to dIdt: positive CURRENT CHANGE causes positive VOLTAGE, negative current change causes negative voltage. The ratio is the L. The coil can be charged with current and it can be discharged, -> it stores energy in magnetic form and it can give back this magnetic energy. For example: If we charge a coil at 100V to 10A in 1 micro sec., it will be discharged at -200V in 0,5 micro sec. (and the inductance is L=U/(dIdt)=100V/(10A/1micro sec.)=10 micro Henry).
In the BCA, the transistors are swithed on and off for equal length of time at 0V output. In the transistors' on-state the coils are switched to the supply voltage, thus their current are rising linearly (*) with a rate of Upsu/L. When the transitors being switched off, the coils are swapping polarity (cause of dIdt -> dFidt -> U change) and their current can be discharged to the power supply because of the clamper diodes (they give back their energy to the PSU). The value of voltage during the charging and the discharging is equal, the coils can be discharged in a length of time they were charged. If the two coil is equal in inductance the output voltage will be constantly 0V during this charging, swapping, and discharging. But the gate drivers can switch the FETs to on-state rapidly than they can switch the FETs to off-state. Thus the length of on-state will be longer. This causes the coils have more time to charge than to discharge, thus there will be a residual amount of current from each discharging cycle -> the coils run over, run over and recirculates huge currents to the PSU (in the simulator, in the practice they will rather acts as a short because of the core saturation). I think these large currents caused the large power losses in your simulation.
(*): linearity depends on the core's magnetisation. The magnetic materials don't have linear magnetisation curves, by chance of near-linear
When the input is positive, the upper side's transistor will be switched on for longer time, and the lower side's transistor will be switched off for shorter time, and a balance will be set at a higher output voltage between the coils' charge and discharge.
The apparent halved inductance caused by the current changing of the coils. When the upper coil's current is rising, the lower coil's current is falling -> dIdt will be twice for the output.
The effect were in the simpulation also shouldn't be appear in the practice using a good gate driver because every component has losses which are swallowing up the energy would be residual. These losses: Rds/on/ (FET), Cds (FET), Uf (diodes), histeresis of the core, resistance of the traces and of every wire. The Cds is a loss factor because it's charge will be discharged and converted to heat by the transistor. Parallel connected resistors with the coils can help to adjust precisely the colis' discharged energy (at the given temperature)
In the end: It's hard to set the transistors' proper on-time length of the because of the possibility of current overrun and the thermal change. Some months ago I thought about the torsition factors of the early discharged coils. It's a nice work. :worm:
I have to go back again for a few month. Thank you for your help and goog luck!
Gyula
Thank you for yor help about the shops, I will inquire which components are obtainable. I looked out the APT30SC60B for the PFC, and found good IGBTs at fairchild for the PSU and the PFC like the FGH50N6S2D. The hard switched topology can be made easily with the UCC3818 and the SiC. And it can be fast switched like a mud because of the nonexistent charge storing effect at the N-P boundary (the N-P boundary is nonexistent in the schottky
)I can't try the simulation because I haven't got Spice simulator, I should to download one. BUT I try to find the cause of fault on the way it works.. On behalf of understanding it's necessary to be familiar with the operation of inductances. I write the formulas in SI. One formula is enough for the BCA: dIdt=U/L where d means derive. So the rate of change of the current flowing across the inductance is equal to the quotient of Voltage switched to it and the value of inductivity. Switching an inductance parallel to a voltage generator the current flowing across the inductance is rising at the rate of change: U/L. Here the U is positive. With the removal of the Voltage gen., the current willn't be disappeared, just the direction of it's change will be opposite: the current will be falling. The inductance's voltage polarity will also be opposite, for it's attitude there is an another formula for the coil's voltage: U=n*dFidt where Fi is the magnetic flux. Fi=B*A, so Fi=(mo*mr*I*n)/l where mo: perbeability of air, mr: permeability of the material, I: the current flowing in the coil, n: number of turns of the coil, l: the magnetic path length. In normal condition the current can be changed, so it causes the change of magnetic flux (Fi). In this way dFidt is proportional to dIdt: positive CURRENT CHANGE causes positive VOLTAGE, negative current change causes negative voltage. The ratio is the L. The coil can be charged with current and it can be discharged, -> it stores energy in magnetic form and it can give back this magnetic energy. For example: If we charge a coil at 100V to 10A in 1 micro sec., it will be discharged at -200V in 0,5 micro sec. (and the inductance is L=U/(dIdt)=100V/(10A/1micro sec.)=10 micro Henry).
In the BCA, the transistors are swithed on and off for equal length of time at 0V output. In the transistors' on-state the coils are switched to the supply voltage, thus their current are rising linearly (*) with a rate of Upsu/L. When the transitors being switched off, the coils are swapping polarity (cause of dIdt -> dFidt -> U change) and their current can be discharged to the power supply because of the clamper diodes (they give back their energy to the PSU). The value of voltage during the charging and the discharging is equal, the coils can be discharged in a length of time they were charged. If the two coil is equal in inductance the output voltage will be constantly 0V during this charging, swapping, and discharging. But the gate drivers can switch the FETs to on-state rapidly than they can switch the FETs to off-state. Thus the length of on-state will be longer. This causes the coils have more time to charge than to discharge, thus there will be a residual amount of current from each discharging cycle -> the coils run over, run over and recirculates huge currents to the PSU (in the simulator, in the practice they will rather acts as a short because of the core saturation). I think these large currents caused the large power losses in your simulation.
(*): linearity depends on the core's magnetisation. The magnetic materials don't have linear magnetisation curves, by chance of near-linear
When the input is positive, the upper side's transistor will be switched on for longer time, and the lower side's transistor will be switched off for shorter time, and a balance will be set at a higher output voltage between the coils' charge and discharge.
The apparent halved inductance caused by the current changing of the coils. When the upper coil's current is rising, the lower coil's current is falling -> dIdt will be twice for the output.
The effect were in the simpulation also shouldn't be appear in the practice using a good gate driver because every component has losses which are swallowing up the energy would be residual. These losses: Rds/on/ (FET), Cds (FET), Uf (diodes), histeresis of the core, resistance of the traces and of every wire. The Cds is a loss factor because it's charge will be discharged and converted to heat by the transistor. Parallel connected resistors with the coils can help to adjust precisely the colis' discharged energy (at the given temperature)
In the end: It's hard to set the transistors' proper on-time length of the because of the possibility of current overrun and the thermal change. Some months ago I thought about the torsition factors of the early discharged coils. It's a nice work. :worm:
I have to go back again for a few month. Thank you for your help and goog luck!
Gyula
hehe
.Hi Timo,
from your schematics I can`t see why are you talking about BCA ( balanced current amplifier ) output stage. What you have here is fairly common half bridge stage with small inductors to prevent shoot through current at zero deadtime. To get real BCA you need to increase L2 and L3 to 22uH, short L4 and get proper modulation signals to the gates of the Mosfets (in BCA, Fets are on at the same time at zero modulation index). To gain some grasp how BCA works, you will have to include PWM modulator in your simulation and simulate over some tens of switching cycles. For such simulations I usually use S (switch) element instead of Mosfets. Seems that there is SW element in LTspice that could have the same function.
Best regards,
Jaka Racman
from your schematics I can`t see why are you talking about BCA ( balanced current amplifier ) output stage. What you have here is fairly common half bridge stage with small inductors to prevent shoot through current at zero deadtime. To get real BCA you need to increase L2 and L3 to 22uH, short L4 and get proper modulation signals to the gates of the Mosfets (in BCA, Fets are on at the same time at zero modulation index). To gain some grasp how BCA works, you will have to include PWM modulator in your simulation and simulate over some tens of switching cycles. For such simulations I usually use S (switch) element instead of Mosfets. Seems that there is SW element in LTspice that could have the same function.
Best regards,
Jaka Racman
Hi!
Does anybody know the requirements of IEC 61000-3-2 (230V up to 16A) and IEC-61000-3-4 (230V above 16A) for the power distribution systems?
Timo, the things seems to be getting along. I could order a Ferroxcube TX63/38/25-3F3 core instead of EPCOS 63/38/25, it seems to be ideal 192 kHz fsw. The Magnetics 77908-A7 Kool Mu is obtainable for 27 EUR/piece at a minimum of 5 pieces per order. The FGH50N6S2D might be obtainable in pack quantity, but if it's not, the IRGP50B60PD1 will done for 220 EUR/ 25 piece. The C-MAC is orderable only at a minimum of 100 pieces unfortunately, but these are 0.5 ppm accurate 24.576 MHz clocks. Maybe the APT30SC60B will be inaccessible, I'm going to ask it today or tomorrow. The Kool Mu core was the critical point prior to the APT SiC. Super-MSS, Hi-Flux or Iron powder would be act as a boiler.
Thank you for your help offer!
Gyula
Does anybody know the requirements of IEC 61000-3-2 (230V up to 16A) and IEC-61000-3-4 (230V above 16A) for the power distribution systems?
Timo, the things seems to be getting along. I could order a Ferroxcube TX63/38/25-3F3 core instead of EPCOS 63/38/25, it seems to be ideal 192 kHz fsw. The Magnetics 77908-A7 Kool Mu is obtainable for 27 EUR/piece at a minimum of 5 pieces per order. The FGH50N6S2D might be obtainable in pack quantity, but if it's not, the IRGP50B60PD1 will done for 220 EUR/ 25 piece. The C-MAC is orderable only at a minimum of 100 pieces unfortunately, but these are 0.5 ppm accurate 24.576 MHz clocks. Maybe the APT30SC60B will be inaccessible, I'm going to ask it today or tomorrow. The Kool Mu core was the critical point prior to the APT SiC. Super-MSS, Hi-Flux or Iron powder would be act as a boiler.
Thank you for your help offer!
Gyula
Hi Frank,
You can configure D-Type Flip Flops (FF) as clock dividers; each FF divides by 2, so by cascading you can divide by 2, 4, 8 etc.
Here's a "divide by 4" example using x2 74’s – I use single packaged FF's by default, but it easier to get the dual 74VHC74 – you will have to change the pin connections for the dual package – and of course you only have one set of Power and Ground connections.
John
You can configure D-Type Flip Flops (FF) as clock dividers; each FF divides by 2, so by cascading you can divide by 2, 4, 8 etc.
Here's a "divide by 4" example using x2 74’s – I use single packaged FF's by default, but it easier to get the dual 74VHC74 – you will have to change the pin connections for the dual package – and of course you only have one set of Power and Ground connections.
John
Attachments
Great!
Thanks again John!
The design of the 1703/ 3103/5015 / 5182 is in progress. Will post them when they somewhat ready.
By dividing the freq. serial to 25 mhz in two steps (cascading), no propagation delay with respect to the hfclk will occur?
Or is this amount not significant? (In fact I was looking for a parallel FF config, due to the prop. delay)
Oh, another thing. Got the Phaselink samples. TI does not provide much info regarding the HFCLK input of the 5015. So can one glue the P661 and the hfclk together? Or is an extra buffer necessary?
Hope to hear from you soon!
Cheers, Frank
Thanks again John!
The design of the 1703/ 3103/5015 / 5182 is in progress. Will post them when they somewhat ready.
By dividing the freq. serial to 25 mhz in two steps (cascading), no propagation delay with respect to the hfclk will occur?
Or is this amount not significant? (In fact I was looking for a parallel FF config, due to the prop. delay)
Oh, another thing. Got the Phaselink samples. TI does not provide much info regarding the HFCLK input of the 5015. So can one glue the P661 and the hfclk together? Or is an extra buffer necessary?
Hope to hear from you soon!
Cheers, Frank
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