Hi John,
I am still digesting your post. I would like to have this modulator board error free, and make hand modifications only on the mother board. So far, I have thought I have a nice design with all traces on the top layer and totally unbroken bottom ground plane. Also all decoupling caps have direct connection to power pins and I have guard ring around PLL part.
On board, i have place only for 5x7mm SMD oscillator. If I would know which one to use, I would definetly put it there. I thought I could achieve the same results with remote oscillator and some sort of clock signal shaping circuit. Since it seems that low phase noise oscillator also requires low noise power supply, I thought to leave this to experimenting on motherboard.
If I stay with remote oscillator, I intend to benefit from your experience. So far, I have ruled LVDS out. You have used parts that are almost 10 times faster than those I intended to use, but also those parts have relatively bad eye pattern in their datashets. I thought of using them, since they have the same pinout as SOT23-5 comparators. PECL also seems to be too fast and requires controlled impedance PCB design.
That leaves me with a comparator or UHC inverters. Regarding UHC, how long were your clock traces?
On the other hand, there are some nice jitter numbers for comparators (15/11 ps RMS - LT1719 datasheet, 1ps RMS for AD8611 measured by Maxim Kochkurov). With comparator, I could even use bandpass filter at the input. I guess I still have some thinking to do. In particular, I will wait to see what Werewolf has to say about jitter in ASCR.
I have now moved PWM series termination resistors from motherboard to the modulator board. The board is now a little larger, so it will be possible to add some more components.
Best regards,
Jaka Racman
I am still digesting your post. I would like to have this modulator board error free, and make hand modifications only on the mother board. So far, I have thought I have a nice design with all traces on the top layer and totally unbroken bottom ground plane. Also all decoupling caps have direct connection to power pins and I have guard ring around PLL part.
On board, i have place only for 5x7mm SMD oscillator. If I would know which one to use, I would definetly put it there. I thought I could achieve the same results with remote oscillator and some sort of clock signal shaping circuit. Since it seems that low phase noise oscillator also requires low noise power supply, I thought to leave this to experimenting on motherboard.
If I stay with remote oscillator, I intend to benefit from your experience. So far, I have ruled LVDS out. You have used parts that are almost 10 times faster than those I intended to use, but also those parts have relatively bad eye pattern in their datashets. I thought of using them, since they have the same pinout as SOT23-5 comparators. PECL also seems to be too fast and requires controlled impedance PCB design.
That leaves me with a comparator or UHC inverters. Regarding UHC, how long were your clock traces?
On the other hand, there are some nice jitter numbers for comparators (15/11 ps RMS - LT1719 datasheet, 1ps RMS for AD8611 measured by Maxim Kochkurov). With comparator, I could even use bandpass filter at the input. I guess I still have some thinking to do. In particular, I will wait to see what Werewolf has to say about jitter in ASCR.
I have now moved PWM series termination resistors from motherboard to the modulator board. The board is now a little larger, so it will be possible to add some more components.
Best regards,
Jaka Racman
Hi Jaka,
Yes, I noticed that you had correctly decoupled the PSU to their respective ground connections on the IC’s. It all to common to see PCB designs where the decoupling caps are connected to VCC but with impossibly long connections to there relevant ground pins…
Like ECL, LVDS also requires controlled PCB impedances.
As the PCB I modified to UHS CMOS clock distribution was originally designed for LVDS, the PCB tracking was far longer then desirable using CMOS transmission - about 150mm @ 100MHz, but still it performed better then LVDS - the CMOS was series terminated.
Your comments about the XO clock deserve further comment. There’s little point in having an ultra low noise supply for the XO, only to have a poor quality supply to the modulator. The PLL and clock distribution in the modulator also requires the same care and attention – not to mention the modulators output section which powers the final PWM reference Latch’s and output pin drivers.
Also, it’s a bad idea to have separate supplies to the XO and the modulator as any noise on these supplies will no longer be seen as common-mode by the modulator. Operate the XO and modulators PLL / Clock sections from the same low noise supplies.
The little modulator PCB should contain the Modulator, SRC, XO & Low noise supplies for modulator + XO.
Use a discrete transistor Pierce XO with a single transistor gain stage as the logic level buffer.
Below is the offending PCB, you can see it heavily modified with the PhaseLink XO BD, with the PWM referance Latches and there PSU under the copper screening tins (notice a CMOS clock length of about 125mm), above the tins, the 200W output stage, with no heat sink – just 2 ounce copper PCB. Also, notice the TAS5015 modulator on the small plug-in PCB in the lower of the picture.
Yes, I noticed that you had correctly decoupled the PSU to their respective ground connections on the IC’s. It all to common to see PCB designs where the decoupling caps are connected to VCC but with impossibly long connections to there relevant ground pins…
Like ECL, LVDS also requires controlled PCB impedances.
As the PCB I modified to UHS CMOS clock distribution was originally designed for LVDS, the PCB tracking was far longer then desirable using CMOS transmission - about 150mm @ 100MHz, but still it performed better then LVDS - the CMOS was series terminated.
Your comments about the XO clock deserve further comment. There’s little point in having an ultra low noise supply for the XO, only to have a poor quality supply to the modulator. The PLL and clock distribution in the modulator also requires the same care and attention – not to mention the modulators output section which powers the final PWM reference Latch’s and output pin drivers.
Also, it’s a bad idea to have separate supplies to the XO and the modulator as any noise on these supplies will no longer be seen as common-mode by the modulator. Operate the XO and modulators PLL / Clock sections from the same low noise supplies.
The little modulator PCB should contain the Modulator, SRC, XO & Low noise supplies for modulator + XO.
Use a discrete transistor Pierce XO with a single transistor gain stage as the logic level buffer.
Below is the offending PCB, you can see it heavily modified with the PhaseLink XO BD, with the PWM referance Latches and there PSU under the copper screening tins (notice a CMOS clock length of about 125mm), above the tins, the 200W output stage, with no heat sink – just 2 ounce copper PCB. Also, notice the TAS5015 modulator on the small plug-in PCB in the lower of the picture.
Attachments
version 1.01.What I'd be interested in is a digital preamp. I'd want it to have a VFD or LCD display, which would display the volume in dB when adjusted, and an oscope-like display which will display the waveform (possibly have two waveforms for stereo, this way you have a visual indication of sound as well). Any project like this that exists?
It's not a world standard, but a good toy. I recommend to use this version!
Hi John,
You have convinced me. Now let's see what TI says about modulator design:
I think PCB design must give justice to such attention to detail in chip design. So for decoupling I intend to use 100nF in parallel with 150uF Panasonic SP caps. These are better than Oscons and have only 12mOhm ESR. Each blocking capacitor pair has series resistor in positive line. This resistor could be exchanged for inductor or 0R jumper, whatever will give best results.
For modulator supply I intend to use National LM2937-3.3 fixed regulator. It has almost flat ripple rejection up to 1MHz and is stable with extremly low ESR capacitors.
I also agree that XO and PLL should have the same supply. First there is question of separate grounds. In TAS5076-5182 evaluation board PLL ground is isolated from system ground with 1R resistor. I will probably copy this, since this resistor could be exchanged by 0R jumper. For XO I will use discrete Pierce oscillator or maybe PhaseLink P602-89C. (If I can get hold of it.)
I am unsure about XO-PLL power supply. TI evaluation board uses separate TPS79133 regulator with additional PI C-LR-C filter at the output. I do not think this regulator is very good and I am open for alternatives. Maybe existing LM2937 could be used with additional heavy passive filtering.
Best regards,
Jaka Racman
You have convinced me. Now let's see what TI says about modulator design:
I think PCB design must give justice to such attention to detail in chip design. So for decoupling I intend to use 100nF in parallel with 150uF Panasonic SP caps. These are better than Oscons and have only 12mOhm ESR. Each blocking capacitor pair has series resistor in positive line. This resistor could be exchanged for inductor or 0R jumper, whatever will give best results.
For modulator supply I intend to use National LM2937-3.3 fixed regulator. It has almost flat ripple rejection up to 1MHz and is stable with extremly low ESR capacitors.
I also agree that XO and PLL should have the same supply. First there is question of separate grounds. In TAS5076-5182 evaluation board PLL ground is isolated from system ground with 1R resistor. I will probably copy this, since this resistor could be exchanged by 0R jumper. For XO I will use discrete Pierce oscillator or maybe PhaseLink P602-89C. (If I can get hold of it.)
I am unsure about XO-PLL power supply. TI evaluation board uses separate TPS79133 regulator with additional PI C-LR-C filter at the output. I do not think this regulator is very good and I am open for alternatives. Maybe existing LM2937 could be used with additional heavy passive filtering.
Best regards,
Jaka Racman
Hi Jaka,
Sorry for my slow response, I’m pulling my hair out trying to complete a PCB design, don’t even care to think how many weeks its over due…
After spending much time comparing the performance of linear regulators (by FFT), I’ve concluded that they are all poor with regards to noise and output impedance.
Here’s my solution, a simple LPF / Opamp / EF. It deserves little circuit description, but anyway here are some notes.
The Vref pin is the required Output voltage; its maximum depends on the input CM range of the Opamp. I normally use a standard regulator as the reference input source; its noise contribution is filtered by the LPF R1, C4.
Don’t send too much time worrying about the noise performance of the Vref, as its completely filtered by R1, C4 – as I said I use 78XX / LM317 type regulators to provide the “Reference”
D1 charges up C4 quickly to about 150mV of Vref, where R1 then takes over and provides the filtering.
R2, C5 stabilise the FB loop at HF, I’ve not spent much time “tuning” these values, as circuit performance is limited by thermal noise.
The Collector voltage on Q1 is supplied by a Pre regulated supply say from a 78XX or 317 type Regulator - at least 3V to 4V higher then Vref, this voltage also powers the Op-amp.
The feedback is TAKEN FROM THE critical node – say the power pin of the IC. So lets say the above circuit powers the PLL Vcc on the TAS, the output of the regulator feeds the PLL’s Power Pad, AND THE REAR off the IC PAD is used as the Feedback pick-up point. This way the regulator senses the true voltage and noise as seen by the PLL. For ultimate performance, it would be better to sense the voltage on the Die - but in this case, we have no access to this point…
The noise of the circuit is lower then –155dB Rel say 5V, from 50Hz, and is limited by the 5534, which is very low noise.
The output impedance - being actively reduced by the Open Loop gain of the 5534 is lower than the typical PCB Copper tracking, and certainly much less then the IC package impedance.
Very simple – and not easily bettered, sure an AD797 gives a little lower LF noise, but its greater then –155dB already!!
A great advantage of the circuit is as the output impedance is extremely low across the entire audio band due to the active FB; the quality of the bulk decoupling capacitors becomes less critical i.e. less capacitor sound "signature".
Sorry for my slow response, I’m pulling my hair out trying to complete a PCB design, don’t even care to think how many weeks its over due…
After spending much time comparing the performance of linear regulators (by FFT), I’ve concluded that they are all poor with regards to noise and output impedance.
Here’s my solution, a simple LPF / Opamp / EF. It deserves little circuit description, but anyway here are some notes.
The Vref pin is the required Output voltage; its maximum depends on the input CM range of the Opamp. I normally use a standard regulator as the reference input source; its noise contribution is filtered by the LPF R1, C4.
Don’t send too much time worrying about the noise performance of the Vref, as its completely filtered by R1, C4 – as I said I use 78XX / LM317 type regulators to provide the “Reference”
D1 charges up C4 quickly to about 150mV of Vref, where R1 then takes over and provides the filtering.
R2, C5 stabilise the FB loop at HF, I’ve not spent much time “tuning” these values, as circuit performance is limited by thermal noise.
The Collector voltage on Q1 is supplied by a Pre regulated supply say from a 78XX or 317 type Regulator - at least 3V to 4V higher then Vref, this voltage also powers the Op-amp.
The feedback is TAKEN FROM THE critical node – say the power pin of the IC. So lets say the above circuit powers the PLL Vcc on the TAS, the output of the regulator feeds the PLL’s Power Pad, AND THE REAR off the IC PAD is used as the Feedback pick-up point. This way the regulator senses the true voltage and noise as seen by the PLL. For ultimate performance, it would be better to sense the voltage on the Die - but in this case, we have no access to this point…
The noise of the circuit is lower then –155dB Rel say 5V, from 50Hz, and is limited by the 5534, which is very low noise.
The output impedance - being actively reduced by the Open Loop gain of the 5534 is lower than the typical PCB Copper tracking, and certainly much less then the IC package impedance.
Very simple – and not easily bettered, sure an AD797 gives a little lower LF noise, but its greater then –155dB already!!
A great advantage of the circuit is as the output impedance is extremely low across the entire audio band due to the active FB; the quality of the bulk decoupling capacitors becomes less critical i.e. less capacitor sound "signature".
Attachments
Hi Jaka,
C1 on my earlier posting should have been 100nF, U1’s pin numbers are incorrect & a FMMT617 can be used at lower current levels.
As the OPAMP can directly supply (and sink) up to 30mA for low current applications, it can be used without Q1. If Q1 is not used then R2, C5 are also no longer needed, but in this instance keep the FB traces as short as possible – a good idea in any case.
Here’s the circuit for up to 30mA, again the same principle for the “Vref” filtering and FB Kelvin sense as earlier.
R92 limits input stage current in case of O/P short Circuit - thereby preventing damage to the internal protection diodes. Its value should be kept as low as possible to prevent unfiltered thermal noise - but high enough to limit IP current during S/C. It should also have been fitted in my ealier post.
C1 on my earlier posting should have been 100nF, U1’s pin numbers are incorrect & a FMMT617 can be used at lower current levels.
As the OPAMP can directly supply (and sink) up to 30mA for low current applications, it can be used without Q1. If Q1 is not used then R2, C5 are also no longer needed, but in this instance keep the FB traces as short as possible – a good idea in any case.
Here’s the circuit for up to 30mA, again the same principle for the “Vref” filtering and FB Kelvin sense as earlier.
R92 limits input stage current in case of O/P short Circuit - thereby preventing damage to the internal protection diodes. Its value should be kept as low as possible to prevent unfiltered thermal noise - but high enough to limit IP current during S/C. It should also have been fitted in my ealier post.
Attachments
Hi John,
thanks for the circuit. I see it as an example of capacitance multiplier circuit. I will try to implement it. My concern would be that long feedback line would act as an antenna and I would get error because of RF rectification. Layout will be very difficult. I must check some articles about HF noise errors in opamps. I will also have to check if opamp is stable into 150uF/12mOhm load.
Best regards,
Jaka Racman
thanks for the circuit. I see it as an example of capacitance multiplier circuit. I will try to implement it. My concern would be that long feedback line would act as an antenna and I would get error because of RF rectification. Layout will be very difficult. I must check some articles about HF noise errors in opamps. I will also have to check if opamp is stable into 150uF/12mOhm load.
Best regards,
Jaka Racman
HI Jaka, Tiki
Your quite correct in being concerned about RF IMD effects on any “non-linear” circuit.
I’ve used the circuit topology for 10 years now, and in that time only once have I seen RF affecting the noise floor. The 5532/4 have proved to perform very well in the presence of RF. I’ve also found that newer breads of “Super Opamps” perform much worse – to a point where I no longer try using them.
I’ve found that the AD797 in unity gain applications oscillates at about 500MHz – 100uV and greater, even with the “Series Damping” resister in the FB loop as described by AD. Due to the HF and low level of this oscillation, its not visible on a Scope, I only found it with a RF Spectrum analyser. The PSU was well decoupled – I still have not been able to use the AD797 in unity gain application with satisfactory results.
In the case of the RF IMD induced “5dB Noise Floor” modulation with the 5534, I cured the problem by placing a 100pF cap next to the IC across the FB loop. This was only observed in the configuration without the EF current buffer. I guess the RC loop stabilisation components help here.
Now when I use the 5534 without the EF buffer, and with a long FB connection, I always place a 100pF cap across the FB loop as close as possible to the IC – my error for not showing it on the circuit.
Below is a typical FFT of a 5V output regulator, with 0dB scale referenced to 5V. The designed was based on the second circuit (but the addition of the EF buffer does not effect the noise floor). The regulator is driving a reference latch Clocked at 33.868MHz. The mains harmonics are due to analyser and test set-up - notice the very low & flat noise floor.
Your quite correct in being concerned about RF IMD effects on any “non-linear” circuit.
I’ve used the circuit topology for 10 years now, and in that time only once have I seen RF affecting the noise floor. The 5532/4 have proved to perform very well in the presence of RF. I’ve also found that newer breads of “Super Opamps” perform much worse – to a point where I no longer try using them.
I’ve found that the AD797 in unity gain applications oscillates at about 500MHz – 100uV and greater, even with the “Series Damping” resister in the FB loop as described by AD. Due to the HF and low level of this oscillation, its not visible on a Scope, I only found it with a RF Spectrum analyser. The PSU was well decoupled – I still have not been able to use the AD797 in unity gain application with satisfactory results.
In the case of the RF IMD induced “5dB Noise Floor” modulation with the 5534, I cured the problem by placing a 100pF cap next to the IC across the FB loop. This was only observed in the configuration without the EF current buffer. I guess the RC loop stabilisation components help here.
Now when I use the 5534 without the EF buffer, and with a long FB connection, I always place a 100pF cap across the FB loop as close as possible to the IC – my error for not showing it on the circuit.
Below is a typical FFT of a 5V output regulator, with 0dB scale referenced to 5V. The designed was based on the second circuit (but the addition of the EF buffer does not effect the noise floor). The regulator is driving a reference latch Clocked at 33.868MHz. The mains harmonics are due to analyser and test set-up - notice the very low & flat noise floor.
Attachments
The LM317 is a still considered “Low Noise”, but even with good decoupling peaks at about 1KHz, the frequency of this peak depends on the output current. I would not worry too much about RF IMD in the 5534 circuit when you observe such behaviour from standard regulators.
100uF+100nF C I/P, C O/P & Cadj
Belows an FFT of a LM317 with 100uF+100nF C I/P, C O/P & Cadj, Vout 5V, No Load, Vref 5V.
100uF+100nF C I/P, C O/P & Cadj
Belows an FFT of a LM317 with 100uF+100nF C I/P, C O/P & Cadj, Vout 5V, No Load, Vref 5V.
Attachments
Hello,
thank you again for your help.
If you are interested, here is the next try for "my" NBDD-design. Not ready yet, but near to be converted to a PCB.
The simulation of the NBDD-principle worked after the update to Orcad 10.0 (university-license) including a new PSpice-Version. It was actually possible to add a primitive but stable global feedback.
I will add a feedback for compensating deadtime and other variations. But first I have to learn a bit more about the cascaded feedback like leapfrog etc.
Regards, Timo
thank you again for your help.
If you are interested, here is the next try for "my" NBDD-design. Not ready yet, but near to be converted to a PCB.
The simulation of the NBDD-principle worked after the update to Orcad 10.0 (university-license) including a new PSpice-Version. It was actually possible to add a primitive but stable global feedback.
I will add a feedback for compensating deadtime and other variations. But first I have to learn a bit more about the cascaded feedback like leapfrog etc.
Regards, Timo
Hi Timo,
one thing I do not like in your schematic is tying HI and LI inputs together in HIP2101. I think it would be better if you would use complementary drive signals and drive each H bridge totem pole with its own HIP2101. I am not really sure, but I think you might have problems with bootstrap capacitor charging. Second, pay special attention to PWM comparator layout and decoupling. You may even want to split C307 and C308 in half and put one at each comparator input. Also, maybe some emiter follower buffer (Zetex FMMT series) might be useful at the outputs of the HIP2101. And finally, I have never used gate drive inductor without protective Schottky diodes from the gates of the Mosfets to to the driver supply caps. Without them, you will probably get double driver supply voltage (or at least nasty spike) to the gates of the Mosfets.
Best regards,
Jaka Racman
one thing I do not like in your schematic is tying HI and LI inputs together in HIP2101. I think it would be better if you would use complementary drive signals and drive each H bridge totem pole with its own HIP2101. I am not really sure, but I think you might have problems with bootstrap capacitor charging. Second, pay special attention to PWM comparator layout and decoupling. You may even want to split C307 and C308 in half and put one at each comparator input. Also, maybe some emiter follower buffer (Zetex FMMT series) might be useful at the outputs of the HIP2101. And finally, I have never used gate drive inductor without protective Schottky diodes from the gates of the Mosfets to to the driver supply caps. Without them, you will probably get double driver supply voltage (or at least nasty spike) to the gates of the Mosfets.
Best regards,
Jaka Racman
Leapfrog
Hi John,
beg your pardon please, it did function from my home PC.
See under:
http://groups.yahoo.com/group/audioexperiment/files/
Leapfrog Design.pdf
Leapfrog LTspice files.zip
Analogspiceman is the author.
Jaka, thanks at first, give me a few additionally hours to answer, please.
Regards, Timo
Hi John,
beg your pardon please, it did function from my home PC.
See under:
http://groups.yahoo.com/group/audioexperiment/files/
Leapfrog Design.pdf
Leapfrog LTspice files.zip
Analogspiceman is the author.
Jaka, thanks at first, give me a few additionally hours to answer, please.
Regards, Timo
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