Does my latest edit to the ground plane find the better of both worlds? An easier path for load current return away from the regulator components and still having the diode and filter cap pulses 'circulate locally'?
If I run 5A through that Wurth bead its power dissipation is about 380mW or so. If it is in my circuit when the mains power is connected to the in-rush limiter and the filter caps charge up, it only dissipates 9mW in the first second (by which time the in-rush is well and truly over - the inrush limiter switches out after about 310mS). However the peak dissipation pulse is something like 600mW. My presumption is that the thing to be wary of is heat and while peak pulses are high the average is such that it doesn't get too hot but then perhaps I am just guessing.
If I run 5A through that Wurth bead its power dissipation is about 380mW or so. If it is in my circuit when the mains power is connected to the in-rush limiter and the filter caps charge up, it only dissipates 9mW in the first second (by which time the in-rush is well and truly over - the inrush limiter switches out after about 310mS). However the peak dissipation pulse is something like 600mW. My presumption is that the thing to be wary of is heat and while peak pulses are high the average is such that it doesn't get too hot but then perhaps I am just guessing.
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Peufeu's right hand diagram can be even better than he has drawn.
If the Return Plane passes under the Power Input trace, then the high frequencies coming in, mostly travel along the return Plane underneath the Flow trace. It does this better at VHF and less well at HF, at LF it looks for minimum resistance instead of minimum impedance because the inductive part of the impedance is so small at LF.
If the Return Plane passes under the Power Input trace, then the high frequencies coming in, mostly travel along the return Plane underneath the Flow trace. It does this better at VHF and less well at HF, at LF it looks for minimum resistance instead of minimum impedance because the inductive part of the impedance is so small at LF.
I was pointing out that the route shown on Peufeu's diagram is for the lowest resistance.
This only applies to LF.
The HF and VHF signals will look for the lowest impedance route.
That lowest impedance route is substantially under the Flow Trace.
Read what I posted.
I did not say that you needed to make any further modifications.
Originally I said
This only applies to LF.
The HF and VHF signals will look for the lowest impedance route.
That lowest impedance route is substantially under the Flow Trace.
Read what I posted.
I did not say that you needed to make any further modifications.
Originally I said
and you rubbished my comment.
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> Latest with Wurth bead added. Plus modelled line rejection with this added.
Do you really need 160dB PSRR at 100Hz ? Maybe you could drop those power wasting resistors ?...
Yeah that was the idea. I didn't draw the HF path cause it would have made too many doodles.
FYI, here's the output of two DACs using the same chip playing -60 something dBfs sine wave. One has a ground plane, the other does not... can you guess
Do you really need 160dB PSRR at 100Hz ? Maybe you could drop those power wasting resistors ?...
Yeah that was the idea. I didn't draw the HF path cause it would have made too many doodles.
FYI, here's the output of two DACs using the same chip playing -60 something dBfs sine wave. One has a ground plane, the other does not... can you guess
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I attach a chart of line rejection with and without the resistors (no ferrite bead). Seems worth having them, no?
Adding the Wurth ferrite bead is wreaking havoc with transient response. The sim is taking forever and waveform a long time to settle...
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Yeah that's the problem with ferrites, they're inductors, so if you stick them between two caps to make a pi filter, watch your damping factor... you need some resistance somewhere, either the capacitor ESR or an additional resistor, and select the bead with the right amount of inductance, not too much...
The current path is from the (-) terminals of C2, C3, and C4
vertically upwards
to the anodes of D2 and D3.
That is why SGK has implemented a star-on-star topology, taking the "ground" output @ lower left, after the enormous 100Hz diode-is-on-for-a-short-time current pulses. Perhaps you will appreciate this better if SGK reposts the schematic.
The cyan-blue current path shown in post #279 is intentional and deliberate. It keeps the output ground away from the return path of the >10 ampere capacitor charging pulses.
vertically upwards
to the anodes of D2 and D3.
That is why SGK has implemented a star-on-star topology, taking the "ground" output @ lower left, after the enormous 100Hz diode-is-on-for-a-short-time current pulses. Perhaps you will appreciate this better if SGK reposts the schematic.
The cyan-blue current path shown in post #279 is intentional and deliberate. It keeps the output ground away from the return path of the >10 ampere capacitor charging pulses.
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I had tacked onto my last Mouser order a LMC555, MCP1407 and STP27N3LH5. I am trying to understand your proposed wiring of the LMC555 versus that depicted in the data sheet for astable (variable duty cycle oscillator) operation. This is my first time dealing with a CMOS timer.
I understand that it is the charging and discharging of the external capacitor that determines the duty cycle. But in your example, amongst other things, there's no connection to pin 7 (discharge). As I look at the data sheet example I note that for time at output high to equal time at output low then Ra must equal zero and of course if Rb is variable (pot) then the duty cycle becomes adjustable. But in your schematic shouldn't the upper end of the pot be connected to V+ and discharge rather than pin 3 (output)? (and the control voltage left unconnected?)
For the MCP1407, decoupling capacitors are recommended to operate the driver over a wide frequency range. However, in this application a high frequency isn't needed. I therefore presume it is okay to omit such decoupling capacitors in this instance. (Also, I note the MCP1407 has a minimum supply voltage of 4.5V. I guess I can test the 12V and 5V rails and one of these to power the MCP1407 for testing the 3V3 rail.)
Lastly, and I apologise for such a basic question, I have not used pcboard/perfboard/protoboard before. There seems to be a bewildering array of this type of board. Any guidance here would be appreciated.
See if you can find someone nearby who built a Quasimodo test-jig, using the PCBoard layout I supplied. It uses the LMC555 + 1R + 1C astable multivibrator circuit with 50 percent duty cycle. Schematic attached.
Borrow this board, power it up, and put your scope probe on node "OSC" -- it should be a 50.0% duty cycle square wave that swings all the way from GND to Vcc. Put your scope probe on node "RC_NODE" -- it should be the middle piece of an exponential charge / discharge waveform, swinging between (Vcc/3) and (2Vcc/3).
Unlike the bipolar transistor NE555 chip, the CMOS LMC555 chip has a full rail-to-rail driver on the output pin #3. This guaranteed rail-to-rail switching allows precision RC timing circuits that drive their R-C node from the output pin. National Semiconductor (when they existed!) mentioned this in their datasheet (attached), see Figure 12.
Borrow this board, power it up, and put your scope probe on node "OSC" -- it should be a 50.0% duty cycle square wave that swings all the way from GND to Vcc. Put your scope probe on node "RC_NODE" -- it should be the middle piece of an exponential charge / discharge waveform, swinging between (Vcc/3) and (2Vcc/3).
Unlike the bipolar transistor NE555 chip, the CMOS LMC555 chip has a full rail-to-rail driver on the output pin #3. This guaranteed rail-to-rail switching allows precision RC timing circuits that drive their R-C node from the output pin. National Semiconductor (when they existed!) mentioned this in their datasheet (attached), see Figure 12.
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Agh I had in the back of my mind to look at the Quasimodo...but didn't. Silly me. Given I have one, a Quasimodo through hole version, sitting in front of me it would now seem interesting to think about whether it could be used for this. I guess issues include the fact that the NTD4906 isn't heatsinked (and I'm not sure the rest of the circuit from the NTD4906 to the transformer connector can handle the current either).
Shame TI omitted Fig 12 from their data sheet. Thanks.
I will keep digging into perfboard...
PS: I note the Quasimodo schematic mentions Vcc from 2.6V. I thought the MCP1407 required at least 4.5V.
Shame TI omitted Fig 12 from their data sheet. Thanks.
I will keep digging into perfboard...
PS: I note the Quasimodo schematic mentions Vcc from 2.6V. I thought the MCP1407 required at least 4.5V.
Wind down VCC on your Quasimodo and see what piece fails first. I predict it won't be the MCP1407.
I plopped an MCP1407 on a protoboard this afternoon and drove it with a 2 volt sinewave, see attached schematic. Then I slowly dialled down the supply voltage. Below about VCC=1.8 volts, the output duty cycle started getting very distorted. So I snapped a picture at VCC=1.82 volts.
Anyone can repeat this experiment. YOU can repeat this experiment. I predict you'll find that the MCP1407 works quite well at supply voltages well below 4.5 volts.
Why does Microchip insist you must supply their 6 ampere gate driver chip with VCC > 4.5 volts, even though it functions correctly at Vcc = 1.82 volts?
I'll type that again:
Why does Microchip insist you must supply their 6 ampere gate driver chip with VCC > 4.5 volts?
_
I plopped an MCP1407 on a protoboard this afternoon and drove it with a 2 volt sinewave, see attached schematic. Then I slowly dialled down the supply voltage. Below about VCC=1.8 volts, the output duty cycle started getting very distorted. So I snapped a picture at VCC=1.82 volts.
Anyone can repeat this experiment. YOU can repeat this experiment. I predict you'll find that the MCP1407 works quite well at supply voltages well below 4.5 volts.
Why does Microchip insist you must supply their 6 ampere gate driver chip with VCC > 4.5 volts, even though it functions correctly at Vcc = 1.82 volts?
I'll type that again:
Why does Microchip insist you must supply their 6 ampere gate driver chip with VCC > 4.5 volts?
_
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> Why does Microchip insist you must supply their 6 ampere gate driver chip with VCC > 4.5 volts?
It's probably going to increase output MOSFETs RdsON and burn the chip if you actually use the rated full drive current at the rated maximum frequency. But you're far from doing that.
Some parts are susprisingly stubborn. The other day I "overclocked" a 74AC04 at about 8 volts, that gave a massive increase in drive current and speed.
It's probably going to increase output MOSFETs RdsON and burn the chip if you actually use the rated full drive current at the rated maximum frequency. But you're far from doing that.
Some parts are susprisingly stubborn. The other day I "overclocked" a 74AC04 at about 8 volts, that gave a massive increase in drive current and speed.
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6A is peak with an 18V supply and is consistent with the typical output resistance (high) of 3 Ohms (full operating temperature range). As Vcc falls, output resistance climbs, somewhat exponentially, and the amount of current the device can deliver falls, ultimately failing to meet its specified minimum output current. If this is correct, the corollary is surely that as Vcc falls the time taken to charge the Mosfet gate capacitance lengthens (somewhat exponentially) and rise time increases, again placing a lower limit on desireable Vcc.
Regarding the regulator test... So far we have simulated transient tests in LTspice one-shot mode - one cycle of up then down. The potentiator in your circuit allows one to vary the frequency of monostable load cycling or, rather, 50% duty cycle. Is it necessary to test across a range of frequencies and if so how does one decide on what should be the start and end? If not, then I presume one could use a resistor in place of the potentiator unless it is simply a case of 'why not' use a potentiator and give the circuit some flexibility?
Re the Quasimodo, and it applies to your sketched schematic as well, Fig 12 of the National Semiconductor data sheet provides that the frequency of oscillation f = 1/(1.4RC). R=39k and C=0.15uF which places me a couple of decimal places out from 120Hz. I presume the compensating item is the 10nF capacitor to ground on the 'control voltage' pin. (I now realise I should adjust the settings, and how to, on my Quasimodo for the UK's supply frequency.)
Regarding the regulator test... So far we have simulated transient tests in LTspice one-shot mode - one cycle of up then down. The potentiator in your circuit allows one to vary the frequency of monostable load cycling or, rather, 50% duty cycle. Is it necessary to test across a range of frequencies and if so how does one decide on what should be the start and end? If not, then I presume one could use a resistor in place of the potentiator unless it is simply a case of 'why not' use a potentiator and give the circuit some flexibility?
Re the Quasimodo, and it applies to your sketched schematic as well, Fig 12 of the National Semiconductor data sheet provides that the frequency of oscillation f = 1/(1.4RC). R=39k and C=0.15uF which places me a couple of decimal places out from 120Hz. I presume the compensating item is the 10nF capacitor to ground on the 'control voltage' pin. (I now realise I should adjust the settings, and how to, on my Quasimodo for the UK's supply frequency.)
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