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High quality Raspberry Pi 24bit/384k I2S card
High quality Raspberry Pi 24bit/384k I2S card
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Old 20th June 2020, 06:09 AM   #1
olo111 is offline olo111  Poland
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Default High quality Raspberry Pi 24bit/384k I2S card

Hi all,

I would just like to share my project - raspberry pi 24bit/384k I2S card

Click the image to open in full size.

Here's my page about this project:

alexx DIY audio page

i hope it will be interesting....
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Old 20th June 2020, 07:36 AM   #2
JohnW is offline JohnW  Hong Kong
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Quote:
Originally Posted by olo111 View Post
Hi all,

I would just like to share my project - raspberry pi 24bit/384k I2S card

Click the image to open in full size.

Here's my page about this project:

alexx DIY audio page

i hope it will be interesting....
its very good that you made the RPi the Slave device - this removes the majority of RPI Clock Jitter issues.

The only outstanding advantage of USB is native DSD support - have you got any plans to support DSD?
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Old 20th June 2020, 08:14 AM   #3
edbarx is offline edbarx  Malta
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Please, permit me to ask a question.

You are insisting there is i2S signal jitter on a Raspberry Pi, and since you are posting in mid 2020, I will assume this also involves the latest Raspberry Pi reincarnations.

An i2S bus is a digital data bus: why should it matter if there is jittering? A DAC can buffer that data and convert it back to analogue using a better clock on its own PCB. Why is this not possible?

Post Scriptum:
I use a Raspberry Pi 3B+ with an IQaudIO DAC Pro hat which has quite a remarkable quality.
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Old 20th June 2020, 12:14 PM   #4
BesPav is offline BesPav  Russian Federation
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Quote:
Originally Posted by olo111 View Post
i hope it will be interesting....
Yes, indeed very good!
But why you do not use simple WM8804?
It can provide clocks for RPI being slave and there are already needed RPI driver.
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Old 21st June 2020, 10:55 AM   #5
olo111 is offline olo111  Poland
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@JohnW
Thanks for your reply,
in fact the VHDL code for the DSD version is ready, it can play DSD64 and DSD128 files, but of course only in DoP mode, as there is no dsd hardware on the BCM2711, also Xilinx chip in the dsd-compatible solution is bigger because it has to accommodate for a few more things

@edbarx
Yes, I2S is a fully digital bus, but in almost every dac chips, analog conversion starts on the falling edge LRCK signal.

@BesPav
I'm not using WM8804 because it always uses PLL to generate signals. I want to get signals with as lillte jitter as possible while using common parts.
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Old 21st June 2020, 12:30 PM   #6
TNT is offline TNT  Sweden
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Quote:
Originally Posted by edbarx View Post
An i2S bus is a digital data bus: why should it matter if there is jittering? A DAC can buffer that data and convert it back to analogue using a better clock on its own PCB. Why is this not possible?
Of course it can.

But then you must also make sure the DAC sida can digest any difference in the 2 clock domains i.e. you need a buffer with all what that brings with it.. still, this is certainly how one should do it.

Still, why anyone would like to build a DAC with a Pi radiating all its garbage in close proximity to a delicate DAC is beyond me. But, everyone seem so amazed that a Pi can be used so the seem blinded and go right ahead

//
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Last edited by TNT; 21st June 2020 at 12:34 PM.
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Old 21st June 2020, 03:31 PM   #7
Markw4 is offline Markw4  United States
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Quote:
Originally Posted by edbarx View Post
An i2S bus is a digital data bus: why should it matter if there is jittering? A DAC can buffer that data and convert it back to analogue using a better clock on its own PCB. Why is this not possible?
ESS Sabre dac chips typically are configured to use their internal ASRC to de-jitter incoming I2S. If I2S is already very low jitter then the ASRC can be turned off and the dac chip run in synchronous mode. People who have done carefully listening tests generally find that synchronous mode sounds better. The reason for a difference in sound with or without ASRC is because Sabre internal ASRC is pretty good but not perfect, its designed to be good enough for most dac chip applications. If cost and complexity of implementation is not a major concern then synchronous mode is available for those who prefer the sound with ASRC disabled.

EDIT: Regarding Sabre ASRC, the sound of it is affected by the DPLL_Bandwidth setting in the dac chip I2C registers. ESS recommends to use the lowest DPLL_Bandwidth setting that results in stable playback. Low DPLL_Bandwidth settings sound better, often much better than the default setting, but stability is limited by jitter of incoming I2S.
Lower incoming I2S jitter = possible to improve sound quality by decreasing DPLL_Bandwidth setting. Unfortunately, many Sabre based dac products leave DPLL_Bandwidth at the default setting with no way for the user to change it.

Last edited by Markw4; 21st June 2020 at 03:38 PM.
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Old 21st June 2020, 08:01 PM   #8
BesPav is offline BesPav  Russian Federation
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Quote:
Originally Posted by olo111 View Post
I'm not using WM8804 because it always uses PLL to generate signals. I want to get signals with as lillte jitter as possible while using common parts.
Not so clearly.
Just imagine.
Masterclock goes from DAC via yours preferred galvanic barrier, all circuitry on the digital side doesn't needs jitter-perfect signal, just master timing reference.
Next this masterclock goes to XIN input of WM8804 and it will synthesise BCK and LRCK at a given freq basis, selected at the RPI side x44.1 or x48 kHz and switched generators at the DAC masterclock side via any optocoupler.
Next RPI will output data in the given basis and we pick those data through the galvanic barrier and reclock if needed on the clear low-jitter side.
 

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