Hi again,
I was currently looking at your SPDIF/AES receiver on your blog.
S/PDIF Receiver with the WM8805 | Dimdim's Blog
And I was wondering why you use 110R and 0.1uF in series and why you only do it for one end of the balanced signal. Shouldn't the impedances be balanced?
If they are not balanced the common mode will turn into differential mode and the whole point of balanced would be gone.
I was currently looking at your SPDIF/AES receiver on your blog.
S/PDIF Receiver with the WM8805 | Dimdim's Blog
And I was wondering why you use 110R and 0.1uF in series and why you only do it for one end of the balanced signal. Shouldn't the impedances be balanced?
If they are not balanced the common mode will turn into differential mode and the whole point of balanced would be gone.
Good eye!
Not only is there only a single 0.1u cap in series with Pin 2 when there should also be a second one in series with Pin 3, but the 110R resistor is connected across Pin 2 and GND where it should have been connected across Pin 2 and Pin 3.
These issues were noticed during the actual build, but since I didn't have any s/pdif sources with XLR connections, I didn't bother to fix them, and eventually they were forgotten.
Oh, and one more thing. Officially the WM8805 doesn't even support AES3 at all.
I really prefer the AK4118 to the WM8805. Much easier to control too.
Not only is there only a single 0.1u cap in series with Pin 2 when there should also be a second one in series with Pin 3, but the 110R resistor is connected across Pin 2 and GND where it should have been connected across Pin 2 and Pin 3.
These issues were noticed during the actual build, but since I didn't have any s/pdif sources with XLR connections, I didn't bother to fix them, and eventually they were forgotten.
Oh, and one more thing. Officially the WM8805 doesn't even support AES3 at all.
I really prefer the AK4118 to the WM8805. Much easier to control too.
Hello,
All the individual design around here on attachments using seperated regulators for power lines. But official one only use seperated reg for vrefhl/r.
But as i directly copied from datasheet here below, my english is far from native.
What i understand here below it ask for seperate lines not seperated regulators. They shared same ground plane.
__________________________________________________________
Power lines of VDDL/R should be distributed separately, from the point with low impedance of regulators or other parts.
Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately with low impedance of regulators, etc. maintained.
AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane
__________________________________________________________
Help me please if i miss something here? it is regulated voltage at the end. What could be wrong using same regulator?
All the individual design around here on attachments using seperated regulators for power lines. But official one only use seperated reg for vrefhl/r.
But as i directly copied from datasheet here below, my english is far from native.
What i understand here below it ask for seperate lines not seperated regulators. They shared same ground plane.
__________________________________________________________
Power lines of VDDL/R should be distributed separately, from the point with low impedance of regulators or other parts.
Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately with low impedance of regulators, etc. maintained.
AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane
__________________________________________________________
Help me please if i miss something here? it is regulated voltage at the end. What could be wrong using same regulator?
Good eye!
Not only is there only a single 0.1u cap in series with Pin 2 when there should also be a second one in series with Pin 3, but the 110R resistor is connected across Pin 2 and GND where it should have been connected across Pin 2 and Pin 3.
These issues were noticed during the actual build, but since I didn't have any s/pdif sources with XLR connections, I didn't bother to fix them, and eventually they were forgotten.
Oh, and one more thing. Officially the WM8805 doesn't even support AES3 at all.
I really prefer the AK4118 to the WM8805. Much easier to control too.
I am going to use the AK4118, but it only has SPDIF in. I would have to make a differential line receiver and you already had a great one. I just couldn't really understand the design choices there, but now I do
It is recommended to use a seperate power supply for digital and analog to prevent common impedance coupling. Sure the decoupling capacitors are possible ferrites decouple from digital noise, but seperate regulators are much more effective. We don't want switching noise in our beloved audio now do we
The datasheet might state differently. It implies that it DOES work if you don't use seperate powersupplies, but that doesn't mean it's the best solution.
Nihtila has done quite extensive research on various voltage regulators. I recommend reading his research on his website.
A shared groundplane is ALWAYS recommended. Don't split it like AKM recommends. Splitting the groundplane only causes more problems than it solves (creating dipole antenna's, increasing current loops). If you want to properly prevent common impedance coupling you should try to suppress the RF current (because the groundplane is mostly inductive, switching CURRENTS are the biggest problems). This can be done by placing ferrite beads in the decoupling circuitry and series resistances in the digital datalines (~47-100 Ohms).
It is recommended to use a seperate power supply for digital and analog to prevent common impedance coupling. Sure the decoupling capacitors are possible ferrites decouple from digital noise, but seperate regulators are much more effective. We don't want switching noise in our beloved audio now do we
The datasheet might state differently. It implies that it DOES work if you don't use seperate powersupplies, but that doesn't mean it's the best solution.
Nihtila has done quite extensive research on various voltage regulators. I recommend reading his research on his website.
A shared groundplane is ALWAYS recommended. Don't split it like AKM recommends. Splitting the groundplane only causes more problems than it solves (creating dipole antenna's, increasing current loops). If you want to properly prevent common impedance coupling you should try to suppress the RF current (because the groundplane is mostly inductive, switching CURRENTS are the biggest problems). This can be done by placing ferrite beads in the decoupling circuitry and series resistances in the digital datalines (~47-100 Ohms).
thx for explanation.
Easiest way is probably to use separate regulators at least for VREFL, VREFR, VDDL, and VDDR. From my experience you can share one for DVDD and AVDD. Although if you're spending quite some money on analog regs already, splitting these won't cost much extra.
I shared a regulator between VREFL/VDDL, and another with VREFR/VDDR, one reason being small form factor as one of design goals. That probably caused me lots of 'issues' (not really issues but difficulties ironing out the best performance) I faced later on.
Note that schematics is just one part of the whole thing. Layout is crucial and determines your performance at the end. Your common power impedance etc will depend on the layout. And without measuring you are really just guessing what affects what and how much.
I shared a regulator between VREFL/VDDL, and another with VREFR/VDDR, one reason being small form factor as one of design goals. That probably caused me lots of 'issues' (not really issues but difficulties ironing out the best performance) I faced later on.
Note that schematics is just one part of the whole thing. Layout is crucial and determines your performance at the end. Your common power impedance etc will depend on the layout. And without measuring you are really just guessing what affects what and how much.
Has anyone seen the measurements of the new RME ADI DAC 2 PRO FS?
It uses the AK4493 as DAC, but the performance exceeds the datasheet by a long shot!
2nd and 3rd harmonic at about -130dB!
I noticed that you could exceed the datasheet values based of Nihtila's research, but this isn't a small margin of a hand full of dB's. This is almost 20dB!
I wonder what their implementation looks like.
RME ADI-2 FS Version 2 DAC and Headphone Amp Review | Audio Science Review (ASR) Forum
It uses the AK4493 as DAC, but the performance exceeds the datasheet by a long shot!
2nd and 3rd harmonic at about -130dB!
I noticed that you could exceed the datasheet values based of Nihtila's research, but this isn't a small margin of a hand full of dB's. This is almost 20dB!
I wonder what their implementation looks like.
RME ADI-2 FS Version 2 DAC and Headphone Amp Review | Audio Science Review (ASR) Forum
Archimago (Archimago's Musings) uses the ADC/DAC version for measurements, apparently the ADC in that is great as well.
That distortion is extremely low. May be a particularly good unit as well, of course. I wonder if big elco helps in THD even if not in THD+N. Maybe I should revise some tests as I used THD+N as figure of merit in these and didn't check THD only that often. LT3042 just didn't always seem to like big capacitance at the output but maybe it would be ok.
A few notes on your comparisons though. Datasheet does not give THD but THD+N so it's not 20dB better than DS. THD+N is -115dB which is the same I measure. This is not 0dBFS level yet though and it gets even lower (-117dB) after that in the RME. But often you get better results with higher level. I (and some others) have a knee before 0dBFS so optimal level is slightly lower, here it's also not clear knee although there is a small drop in SINAD at one point.
Nevertheless, excellent results. Seems they have great implementations. In the ADC/DAC one the PCB was I think 10 layers so that pleases engineer as well. Btw, I wonder if they do something in the FPGA and in what mode the DAC is used in.
Hello Tomi, thanks for all that great infos, one thing i want to mentioned the cap you used 100u VCMR. most of the designs even in referance design it is 10u. Is there any particular reason to do that.
Dear Tomi,
When I had bumped in this link, Your bypass experience came into mind (in your 4493 'saga')..
Experimental Comparison of 0402 Ceramic Capacitors as Supply Bypasses
Ciao, George
When I had bumped in this link, Your bypass experience came into mind (in your 4493 'saga')..
Experimental Comparison of 0402 Ceramic Capacitors as Supply Bypasses
Ciao, George
No particular reason. Not sure why I ended up using that
I never played with that cap much; think I did try some options in the beginning but didn't see any differences. I don't think that's very critical. It's the common mode voltage and should cancel out in the output circuit anyway.I also tried to measure effects of different capacitors but couldn't really. Doesn't mean there are no measurable differences but I wasn't able to do that. With such low frequencies we have in audio (even with over-sampling converters) it's not easy to measure such things. Should maybe feed the circuits with higher bandwidth stimulus but then again what would we really be after..
But thinking of higher bandwidth stuff, cap performance is mainly set by its inductance which mostly comes from package size. Thus, smaller package works better in higher frequencies. Moreover, if you parallel these caps you reduce the inductance and make it even better; and also increase capacitance of course.
Henry Ott has some good stuff in his EMC book about bypass caps. He measured impedance across frequency. In your link nothing bad happens when all those different caps are used in parallel (although it doesn't help either), but it may cause very nasty impedance resonance spikes and make things a lot worse. According to Ott's measurements, it is better to parallel the same caps than use different values. In any case, the only way to ensure it works in your application is to measure (which may not be easy).
In my odd cap results there are likely also some very subtle effects going on between different caps I just couldn't measure. The distortion levels in high performance audio are so extremely low that I presume even very tiny things may make a difference in.
Personally I use OPA1612 in my design, but I haven't realised it (I had a very busy year due to my masters program and job).
It depends on the requirements you have. How much noise and how much distortion you tolerate?
The reason I chose the OPA1612 is for it's noise and high open-loop gain. I wanted to make the analog stage have unmeasurably low distortion (it's not the standard differential 2nd order MFB filter). This way I can keep reusing the analog section of my design.
If you need a headphone output then I recommend the OPA1622 as it can deliver significantly higher currents.
I guess i will use same as you, Opa1612. So Could you please share the schematic of your analog stage i do not want to mess up with resistor and capacitor values.
I will not share my schematic (yet). I need some verifications on a real PCB before I want to share. Besides that, I don't know if I want to share the exact schematic (I am considering making it a module).
It is not difficicult to design a MFB low-pass filter. There's even calculators for it! If you want to copy paste a design, you can use the filter in the typical application or you can pay someone (to design it for you or by buying a module).
The architecture I use is slightly different. It was based on a design by Bruno Putzeys that he explained in an AES meeting. It can be found here: https://www.hypex.nl/img/upload/doc/an_wp/WP_AES123BP_the_engineers_survival_guide.pdf
On slide 47.
I use C0G/NP0 and thin-films only in the signal path to minimise non-linearity and microphonics and possible problems with capacitance change over temperature/voltage. Furthermore I aim for a Q = 0.5 (damping = 1), to optimise transient response.
This should allow you to build your own. It's enough to find the transferfunction yourself! All you need is, all be it alot, the KCL. You could also use a control theory approach, but it's a bit more tricky.
It is not difficicult to design a MFB low-pass filter. There's even calculators for it! If you want to copy paste a design, you can use the filter in the typical application or you can pay someone (to design it for you or by buying a module).
The architecture I use is slightly different. It was based on a design by Bruno Putzeys that he explained in an AES meeting. It can be found here: https://www.hypex.nl/img/upload/doc/an_wp/WP_AES123BP_the_engineers_survival_guide.pdf
On slide 47.
I use C0G/NP0 and thin-films only in the signal path to minimise non-linearity and microphonics and possible problems with capacitance change over temperature/voltage. Furthermore I aim for a Q = 0.5 (damping = 1), to optimise transient response.
This should allow you to build your own. It's enough to find the transferfunction yourself! All you need is, all be it alot, the KCL. You could also use a control theory approach, but it's a bit more tricky.
Proper implementation (in this case) requires integration on 1 PCB anyway. You need a large PCB area to provide for proper cooling.
If you really want a module, place the decoupling capacitors on the PCB, allow for SMD heatsink to be mount (if you can find a suitable one) and use the right amount of pins (10pin in this case).