Hi,
I wouldn´t use fixed resistors from the start, but either of two options.
The optimum degree of current source modulation is load dependant.
The poti-setting differs between low-impedance/high load-current loads and high-impedance/low load-current loads and should be set after the lowest load impedance one expects and highest current swing symmetry.
The first option beeing to solder pots permanently.
Bürklin lists a decent range of 3mm², 4mm² SMD multiturn pots from Bourns and BI-Tec as does Digikey with several vendors up to Vishays MetalFoil.
The second using pots provisionally to evaluate the right values and replace them with fixed value resistors permanently.
jauu
Calvin
I wouldn´t use fixed resistors from the start, but either of two options.
The optimum degree of current source modulation is load dependant.
The poti-setting differs between low-impedance/high load-current loads and high-impedance/low load-current loads and should be set after the lowest load impedance one expects and highest current swing symmetry.
The first option beeing to solder pots permanently.
Bürklin lists a decent range of 3mm², 4mm² SMD multiturn pots from Bourns and BI-Tec as does Digikey with several vendors up to Vishays MetalFoil.
The second using pots provisionally to evaluate the right values and replace them with fixed value resistors permanently.
jauu
Calvin
Attachments
sounds goodwhat about embedded self-powering PSU (energy harvesting), wifi remote control,...
Go nuclear (mmm... Germany is scrapping al nuclear
)
Hi,
so far so small ;-)
I´d try to get the In-out connectors all to one side with a single row of connectors.
The thermal for the power transistors may be a bit small. You may increase thermal capacitance by using the second copper layer also by thermal vias.
I´d also try to get the 3 casings of CFP-Master transistors in close proximity and glue a single cooling fin covering all 3. The left CFP-bipolar could switch positions with the passive component to its right. The right hand side CFP-block may be turned 90° counterclock-wise. The LSK shoved upwards, switching positions with the Poti.
Besides getting the 3 active devices close together it´d give way to place the power caps in the middle, closer together, reducing trace length and loop size, hence decrease inductance.
Omit with the T-connection to the lytics/caps. Instead use dedicated to- and from traces (V-shape).
For easy accessability the Potis are usually better placed towards the outer rim of the PCB. To keep most of the signal traces on one copper plane (every via means parasitics) I´d use SMD Pots.
I´d also add small inductances in series ahead of the power caps (e.g 600R@100MHz)
The pic is a cutout from a first attempt for the Hybrid-Compound Buffer (JFET-cascode). Two buffers on a single PCB of 80x40mm. Roughly 1/3rd thermals, 1/3 circuit, 1/3rd power supply lytics.
jauu
Calvin
so far so small ;-)
I´d try to get the In-out connectors all to one side with a single row of connectors.
The thermal for the power transistors may be a bit small. You may increase thermal capacitance by using the second copper layer also by thermal vias.
I´d also try to get the 3 casings of CFP-Master transistors in close proximity and glue a single cooling fin covering all 3. The left CFP-bipolar could switch positions with the passive component to its right. The right hand side CFP-block may be turned 90° counterclock-wise. The LSK shoved upwards, switching positions with the Poti.
Besides getting the 3 active devices close together it´d give way to place the power caps in the middle, closer together, reducing trace length and loop size, hence decrease inductance.
Omit with the T-connection to the lytics/caps. Instead use dedicated to- and from traces (V-shape).
For easy accessability the Potis are usually better placed towards the outer rim of the PCB. To keep most of the signal traces on one copper plane (every via means parasitics) I´d use SMD Pots.
I´d also add small inductances in series ahead of the power caps (e.g 600R@100MHz)
The pic is a cutout from a first attempt for the Hybrid-Compound Buffer (JFET-cascode). Two buffers on a single PCB of 80x40mm. Roughly 1/3rd thermals, 1/3 circuit, 1/3rd power supply lytics.
jauu
Calvin
Attachments
PCB for CFP2 v0.2
Hello all,
here's another version of a small board for CFP2. Overall board size is 48x40mm. Thermal pad area per power transistor is approximately 10x20mm each layer. Could be increased by increasing board size.
Pots are SMD now and placed more to the outer rim, active devices are close together and loop area of pwr supply has been reduced. In and out are on left and right side respectively, out could be moved to the left too if there is any problem with this config. PCB layout is always a compromise
Again, any comments are welcome
MiiB: I am using Target! so posting files wouln't be of much help for you !?
regards, Daniel
Hello all,
here's another version of a small board for CFP2. Overall board size is 48x40mm. Thermal pad area per power transistor is approximately 10x20mm each layer. Could be increased by increasing board size.
Pots are SMD now and placed more to the outer rim, active devices are close together and loop area of pwr supply has been reduced. In and out are on left and right side respectively, out could be moved to the left too if there is any problem with this config. PCB layout is always a compromise
Again, any comments are welcome
MiiB: I am using Target! so posting files wouln't be of much help for you !?
regards, Daniel
Attachments
Last edited: