Zen -> Cen -> Sen, evolution of a minimalistic IV Converter

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#628
There are some questions about why 2SK369V are recommended for the SEN IV for ES9018.

In the original article in Linear Audio VOlume 2, I was describing a design based on the PCM1704, which has a current range of 2mA. The ES9018 has 4x that when used in stereo mode. The article also described in some detail how to determine Zin in both SEN & CEN. When using 4x 2SK170BL per each SEN (half the PCB), the Zin is approximately 15R. It is widely believed that the ES9018 will benefit in a lower Zin, e.g. <10R. To obtain that value, you can use 8x 2SK170BL per SEN, or 4x 2SK369V. Each 2SK369V is approximately equivalent to 2x 2SK170BL.


Patrick



Patrick
 
#631
Felipe,

The 10mA is a typical figure.
What I said in the article is that you do not want to swing more than 25% of bias.
So if you total current swing is say 8mA (as in ES9018), you want to have at least 32mA total bias.

For example, Nic uses a set of 2SK369Vs with Idss of around 17mA.
So two of them in parallel (Q1//Q2, or Q3//Q4) gives about 34mA bias, thus satisfying the above mentioned rule of thumb.

It is important that Q1 has about the same Idss as Q3, and Q2 same as Q4.
Furthermore to have minimum DC offset, Idss of Q1+Q2 should equal Q3+Q4.
On top of that Q1 and Q3 should be glued onto the same heat sink, so that they thermally track each other.
The same applies to Q2 and Q4.

Of course if Idss of alll 4 FETs are exactly identical, you can aloocate them randomly.
For all those who obtain JFET sets from us, they all have a table telling them which JFET to use in which position.

I hope I have made it clearer to you rather than more confusing.

🙂


Patrick
 
#632
EUVL said:
Of course if Idss of alll 4 FETs are exactly identical, you can aloocate them randomly.
Click to expand...

..... and when you have well-matched FETs there is the added benefit that making the voltage divider becomes a question of matching a pair of 1k resistors😀

Before going to the lab this morning I took a little movie to document the DC-offset behaviour and you can see it here. The offset at cold start is about 6.5 mV and drops to about 1/3 mV in a few minutes and remains stable after this. You may be able to spot the pairs of PRP's used to generate the voltage divider.
Enjoy,
Nic
 
#635
NicMac said:
..... and when you have well-matched FETs there is the added benefit that making the voltage divider becomes a question of matching a pair of 1k resistors😀

Before going to the lab this morning I took a little movie to document the DC-offset behaviour and you can see it here. The offset at cold start is about 6.5 mV and drops to about 1/3 mV in a few minutes and remains stable after this. You may be able to spot the pairs of PRP's used to generate the voltage divider.
Enjoy,
Nic
Click to expand...

Very nice & video, your are a very good director😉
Where did you connect the voltage divider & how can I use a 2K trimmer?
I really enjoyed Nic, thanks to post.
Felipe
 
#636
indeed nice numbers!!

i considered the VPG 300198Z matched Zfoil resistor network as a one piece solution to this (1 piece for both channels has 2 separate 2r networks in one part, also great for instrumentation inputs) and who knows i may still end up there. I want to explore active solutions that dont load the AVCC reg first as an exercise; i know that may seem upside down. the load of course will be tiny but still

(I wont use 300198Z, but instead whatever the texas components part assignment is, as they'll sell 1 part while VPG wont)

@ Felipe: you connect a divider across AVCC->ground on each AVCC L/R shunt reg output and tap the junction
 
Last edited:
#637
> Please post here, as an example, what Idss your two sets of JFETs have, and how they are allocated to Q1-Q4.

This is how you suggested me to put them:

Sen 1a
#212 17.01 // #146 17.04
#101 17.01 // #209 17.02

Sen 1b
#168 17.07 // #53 17.12
#60 17.08 // #44 17.10

Sen 2a
#55 17.13 // #1 17.15
#246 17.12 // #202 17.15

Sen 2b
#99 17.22 // #24 17.24
#100 17.22 // #267 17.23

Note that I may have screwed up getting this right as there are two types of heat-sinks involved. I may have gotten away with such an error as my FETs are all within about 1% Idss.

My advice to builders is to take this gluing part of the build seriously and plan it well: test that the FETs fit before preparing the glue (I had to file a tiny bit for 2 out of the 16 FETs). These heat-sinks are remarkable low-tolerance devices!

And have fun to fit all 6 legs into the PCB at the same time:bawling:

Cheers,

Nic
 
#638
> And have fun to fit all 6 legs into the PCB at the same time.

It is actually quite easy.
First you fit the JFETs with their correct allocation on the PCB.
Then you fit the heatsinks on top without glue.
Automatically you have all the legs properly bent.

Then take them out to glue.
Then refit and solder.

QED. 🙂


Patrick
 
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