I'm not the leader here. I leave being "Der Fuehrer" to others. I am confident that the SNR will soon improve. Snowflakes melt away on the kitchen window.
Now, given this project is of zero interest to you, as it doesn't align with your prejudices and you have been told multiple times it will not pander to them either, maybe I can thank you for your contribution to SNR improvements?
Thor
I haven't looked at super caps in forever, I didn't realize they've come this far.
Jocko used to talk about 1/f noise for digital, clocks, D/A chips. This is the regulator he put together and used. I've done this in a number of circuits and have been happy with it. I don't have the gear to measure like he did so I can't comment.
Are you able to conduct an post measurements?
Mike
Jocko used to talk about 1/f noise for digital, clocks, D/A chips. This is the regulator he put together and used. I've done this in a number of circuits and have been happy with it. I don't have the gear to measure like he did so I can't comment.
Are you able to conduct an post measurements?
Mike
Attachments
Yes, me too. I had occasion and would suggest that latest generation low ESR super capacitors are a game changer for a lot in audio.
Yes. I still don't think he is right, but hey.
I have used similar in commercial products. More modern Op-Amp's can often dispense with the pass transistor.
I no longer have access to an AP, an QA box is best I can do. I cannot really measure noise with a charged super capacitor and a few ohm, I can directly at the linear lab power supply.
There are some papers where peeps measure ESR and noise as indicators of lifespan in heavy duty cycle use and I extrapolated from there. And yes, EOL supercap's are more noisy. But the noise frequency is so low, as is the level, its challenging for folks with much better equipment parks than little old me and measure over hours at a time.
Lil olde me figures that's "good enough for government work and audio".
How do you think a clock running from a 3,000,000uF/75mOhm capacitor that is fed DC via 2mH/4R DCR from a 317 regulators will do (given other local bypassing of course)?
This (~ 200nV |/Hz @ 200Hz - plus noise from a 317 has minimal 1/LF rise, it actually calculates from measurements to 150nV|/Hz):
filtered with this:
Less noise than a 5534 for sure. And nobody stops using something lower noise as regulator. Or bigger supercapacitors. It just takes longer to charge.
If I use two of my preferred 25F/2.7V capacitors the general graph looks the same, but we see ~ 12dB noise improvement over the above, -46dB @ 3Hz...
Here is what I use (the factory is in Thailand):
https://www.mouser.com/datasheet/2/129/du_e_p262-1889763.pdf
And yes, the specifications are pessimistic.
Past that, noise conversion of PSU noise into crystal oscillator phase noise is material, but much less than often assumed:
This is from a paper testing a discrete pierce oscillator at 10MHz. Seems 3,000nV|/Hz PSU noise (3uV |/Hz or 1mV of white wideband noise) still get's -146dBc flatband. Mind you, I struggle to recall an oscillator that clocked in at -140dBs at 10Hz offset. I'm happy if I see -90dBc. Maybe Jocko's magic crystal did better?
Thor
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Jocko never had any thing magic that I know of but he did sort. A lot. I have a couple crystals he sent me that are better than anything I've found elsewhere. Again, just sorted for the best.
Your numbers are the best I've seen.
Mike
Your numbers are the best I've seen.
Mike
Yeah, I mean he had a special (long discontinued) affordable crystal that even unsorted was pretty good and sorted even better.
Wow.
A Magic Crystal!
And you won't adam'n'eve it, from Magic Crystal Limited no less.
With an appropriate pricetag of only 350 Bux each and an MOQ of 5 (unless inflation and tariffs strike of course).
That that's a mere 700 Bux for a set of 2, if you can find use for the other 4 sets.
Ho Lee Chit!
I suspect for 16 Bit PCM 90dBc @ 10Hz may be tolerable. That's a Kyocera XO (blue line) that sells for 1.25 USD in singles:
A bit better than 90dB @ 10Hz.
Thor
Ok, so back to our Glock.
Actually, Clock, freudian slip. I made some more changes on supplies and thinking stuff through.
This will be on the large main PCB. For manufacturing ease and cost efficiency I set the following rules:
SMT components single sided ONLY. All vendors hate to run PCB's through reflow twice.
THT components are on the opposite side from SMT. Allow distance to SMT Components for manual soldering of THT components.
4 Layer PCB. On large PCB's 6-Layer get's expensive. Instead put the money into heavier copper and where possible copper filled vias, small enough diameter vias with heavy plating tend to do this by themselves.
Continuous DGND plane everywhere digital and under the TDA1541, but stopping where the TDA1541 power supplies and analogue start (there will be a separate analogue plane there), island pours for separate isolated supplies that maximise area on the layer that get's AGND for TDA1541.
Now a schematic (small modifications from earlier):
This clock generator run's either of local crystal clocks or an MCK supplied by an SPDIF receiver (AK4118 in HW mode or WM880x in SW Mode or whatever) or an MCK supplied by an USB Board.
Default oscillators are Kyocera KCxxxxK series, 2016-3225 preferred over larger versions (larger versions are just adapter PCB's for the 2016 format clock).
There will be footprints and solder jumpers to allow the use of canned DIP clocks like accusilicon or whatever (including the 350 Bux each "Magic Crystal" ones). Personally, I question the validity of very expensive (> 50 Bux probably closer to 10 Bux) clocks for digital audio, I'd like actual solid evidence (not anecdotal tales) that the objective differences between (say) a Kyocera KCxxxxK with > -90dBc at 10Hz offset and a Magic Crytal with -140dBc at 10Hz offset are audible with music recordings.
Power supplies are "super capacitor buffered". I find each active supply has a subtle sound signature. Shunt regulation generally seems preferrable to series regulation, but simple passive LC or RC filtering has been preferrable in my experience. Modern low ESR supercapacitors now allow LC filters that are "next level". So why not use them? This is one of the main differences to anything else out there, supercapacitor supplies everywhere we can. This is DIY and we can do things that would a hard sell for a serious commercial product.
As a supercapacitor bank is basically a dead short at turn on and needs charging, there is a delay after turn-on, before the supplies are ready. I design for ~ 60 Seconds charge-up time. Clocks and complex CMOS IC's dislike slow rising supplies and should be kept in reset while supplies ramp up or get a reset once supplies are sufficient for operation. STM1001R is a common power supervisor that will assert the RST Pin low once the PSU voltage exceeds ~ 0.8V (1V guaranteed across all conditions) and will release RST 0.2 seconds after the IC's Vcc exceeds 2.55...2.7V. This should allow the clocks and all IC's to start up cleanly.
The clock selector and divider is boring, except for one fact, wherever actual clocky thingeys happen either 74F (Fast Schottky TTL derived Logic, really the ultimate bipolar logic, it came so late most peeps - me included - missed it) or super fast UNBUFFERED CMOS.
Now 74F logic is power hungry, limited to "only" ~ 100Mhz and mostly obsolete. Why not use some fancy new CMOS logic?
Without wanting to go into too much details of everything, for truly high quality audio CMOS are a poor choice. We see that in the Bipolar/ECL based DAC's like the TDA1541 and PCM56 are still rated extremely highly for subjective sonics experience (despite VERY pedestrian objective performance) while the latest and greatest's CMOS based based DAC's attract comments like "Sound like a Woke in a Gamelan" or "Hilarious Dummy Sound".
If we look at a comparison of phase noise for different logic families the standouts are ECL, 74F & 74AC(T). Both 74F & ECL being bipolar have higher flat band phase noise (still ~ -150dBc so nothing to loose sleep about) but a much lower 1/LF noise corner. Non of the low voltage stuff compares well.
Out of the above list ECL is the fastest option and is free of ground bounce and most of the things that afflict other logic families, because it's differential logic. But it's extremely power hungry and with the equivalent of a 74xx74 selling at 10USD in volume, well, that get's kinda expensive pretty rapidly.
The 74AC series in notorious for massive issues with ground bounce, so let's just skip that. Not doing heroic layout challenges. I agree with Jocko, don't use 74AC, it's evil.
This leaves 74F as a happy middle ground. It is the next step after 74A(L)S and is faster and uses additional circuitry to ensure the output does not suffer the kind of shoot through current that so heavily plagues CMOS. On top, all logic is non-saturating Bipolar, so it's actually closer to a linear bipolar circuit than a saturated switching one.
The downside is a LOT of static current consumption and the power supply lines are current modulated with the actual frequencies passing through the IC, as opposed to CMOS where each edge sets of a veritable cacophony of switching each with each single inverter in the IC adding it's own little bit of shoot through current as the signal passes through the threshold. Now I think decoupling ~ 25MHz and less sufficiently is a tractable engineering challenge, more than dealing with current spikes measured in picosecnds, so you need a GHz scope to even see anything.
So, I'll leave it here with a Gamelan (minus the woke I hope):
Thor
Actually, Clock, freudian slip. I made some more changes on supplies and thinking stuff through.
This will be on the large main PCB. For manufacturing ease and cost efficiency I set the following rules:
SMT components single sided ONLY. All vendors hate to run PCB's through reflow twice.
THT components are on the opposite side from SMT. Allow distance to SMT Components for manual soldering of THT components.
4 Layer PCB. On large PCB's 6-Layer get's expensive. Instead put the money into heavier copper and where possible copper filled vias, small enough diameter vias with heavy plating tend to do this by themselves.
Continuous DGND plane everywhere digital and under the TDA1541, but stopping where the TDA1541 power supplies and analogue start (there will be a separate analogue plane there), island pours for separate isolated supplies that maximise area on the layer that get's AGND for TDA1541.
Now a schematic (small modifications from earlier):
This clock generator run's either of local crystal clocks or an MCK supplied by an SPDIF receiver (AK4118 in HW mode or WM880x in SW Mode or whatever) or an MCK supplied by an USB Board.
Default oscillators are Kyocera KCxxxxK series, 2016-3225 preferred over larger versions (larger versions are just adapter PCB's for the 2016 format clock).
There will be footprints and solder jumpers to allow the use of canned DIP clocks like accusilicon or whatever (including the 350 Bux each "Magic Crystal" ones). Personally, I question the validity of very expensive (> 50 Bux probably closer to 10 Bux) clocks for digital audio, I'd like actual solid evidence (not anecdotal tales) that the objective differences between (say) a Kyocera KCxxxxK with > -90dBc at 10Hz offset and a Magic Crytal with -140dBc at 10Hz offset are audible with music recordings.
Power supplies are "super capacitor buffered". I find each active supply has a subtle sound signature. Shunt regulation generally seems preferrable to series regulation, but simple passive LC or RC filtering has been preferrable in my experience. Modern low ESR supercapacitors now allow LC filters that are "next level". So why not use them? This is one of the main differences to anything else out there, supercapacitor supplies everywhere we can. This is DIY and we can do things that would a hard sell for a serious commercial product.
As a supercapacitor bank is basically a dead short at turn on and needs charging, there is a delay after turn-on, before the supplies are ready. I design for ~ 60 Seconds charge-up time. Clocks and complex CMOS IC's dislike slow rising supplies and should be kept in reset while supplies ramp up or get a reset once supplies are sufficient for operation. STM1001R is a common power supervisor that will assert the RST Pin low once the PSU voltage exceeds ~ 0.8V (1V guaranteed across all conditions) and will release RST 0.2 seconds after the IC's Vcc exceeds 2.55...2.7V. This should allow the clocks and all IC's to start up cleanly.
The clock selector and divider is boring, except for one fact, wherever actual clocky thingeys happen either 74F (Fast Schottky TTL derived Logic, really the ultimate bipolar logic, it came so late most peeps - me included - missed it) or super fast UNBUFFERED CMOS.
Now 74F logic is power hungry, limited to "only" ~ 100Mhz and mostly obsolete. Why not use some fancy new CMOS logic?
Without wanting to go into too much details of everything, for truly high quality audio CMOS are a poor choice. We see that in the Bipolar/ECL based DAC's like the TDA1541 and PCM56 are still rated extremely highly for subjective sonics experience (despite VERY pedestrian objective performance) while the latest and greatest's CMOS based based DAC's attract comments like "Sound like a Woke in a Gamelan" or "Hilarious Dummy Sound".
If we look at a comparison of phase noise for different logic families the standouts are ECL, 74F & 74AC(T). Both 74F & ECL being bipolar have higher flat band phase noise (still ~ -150dBc so nothing to loose sleep about) but a much lower 1/LF noise corner. Non of the low voltage stuff compares well.
Out of the above list ECL is the fastest option and is free of ground bounce and most of the things that afflict other logic families, because it's differential logic. But it's extremely power hungry and with the equivalent of a 74xx74 selling at 10USD in volume, well, that get's kinda expensive pretty rapidly.
The 74AC series in notorious for massive issues with ground bounce, so let's just skip that. Not doing heroic layout challenges. I agree with Jocko, don't use 74AC, it's evil.
This leaves 74F as a happy middle ground. It is the next step after 74A(L)S and is faster and uses additional circuitry to ensure the output does not suffer the kind of shoot through current that so heavily plagues CMOS. On top, all logic is non-saturating Bipolar, so it's actually closer to a linear bipolar circuit than a saturated switching one.
The downside is a LOT of static current consumption and the power supply lines are current modulated with the actual frequencies passing through the IC, as opposed to CMOS where each edge sets of a veritable cacophony of switching each with each single inverter in the IC adding it's own little bit of shoot through current as the signal passes through the threshold. Now I think decoupling ~ 25MHz and less sufficiently is a tractable engineering challenge, more than dealing with current spikes measured in picosecnds, so you need a GHz scope to even see anything.
So, I'll leave it here with a Gamelan (minus the woke I hope):
Thor
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Ok, onto to the Hai Ente (Shark Duck)...
Here the TDA1541 and it is really meant for very close integration with clock system:
The intention is to have the Clock Generator (and final divider at the TDA1541) act as clock master.
As such, we get a division of our 512X MCK to a 32X (or 16X) BCK. There the idea is that each time we divide our clock by a factor 2, we also reduce phase noise by a factor 2. So for 4X sample rates and running IIS we still get 12dB phase noise reduction.
Thus our ~ -90dBc @ 10Hz offset 1.25 US Dollar Kyocera Clock magically is transformed into a ~ -102dBc at 10Hz offset clock, IF our divider adds minimal phase noise and spurs etc. Both 74AC and 74F logic have been tested (by others) at said levels.
Now we only get this benefit if we divide the 512X MCK. If we directly use MCK for "re-clocking" no dice.
As I want to keep the choice of what goes between a standard IIS input and the circuit above open, the circuit can be configured as clock master for 32X FS or 16X FS BCK. It can also be configured as re-clocker working on a divided MCK (/2/4/8) to reclock simultaneous outputs from FPGA's or CPLD's designed correctly (no stopped clock please). Makes it very messy. In reality I'll put 0402 resistor footprints and thus a solder bubble easily selects. Default stuffing obviously for 32X FS IIS, as this what we can guarantee.
Power supply, Supercapacitors again. I need to add a power supervisor IC, note to self.
Oh and before anyone b!tches about the "noisy TL431" and the "noisy 317" please fully understand and analyse the circuit, so you can understand what it does.
Thor
PS, not sure if I need to explain Hyloidealism. It essentially unifies idealism and materialism. It means we treat certain ideals, that have not been substantiated sufficiently to be classed as confirmed from am materialistic (objectivistic) view, but treat them as if they are actually real anyway and act accordingly. If you look at the circuit and read the comments, the ideals embodied here should be obvious.
Anyone else, please go and listen to your latest CMOS mega-oversampled and ASRC'ed etc. DAC that to some sound like a "Woke in a Gamelan" or "Hilarious Dummy Sound". This is not for you.
Here the TDA1541 and it is really meant for very close integration with clock system:
The intention is to have the Clock Generator (and final divider at the TDA1541) act as clock master.
As such, we get a division of our 512X MCK to a 32X (or 16X) BCK. There the idea is that each time we divide our clock by a factor 2, we also reduce phase noise by a factor 2. So for 4X sample rates and running IIS we still get 12dB phase noise reduction.
Thus our ~ -90dBc @ 10Hz offset 1.25 US Dollar Kyocera Clock magically is transformed into a ~ -102dBc at 10Hz offset clock, IF our divider adds minimal phase noise and spurs etc. Both 74AC and 74F logic have been tested (by others) at said levels.
Now we only get this benefit if we divide the 512X MCK. If we directly use MCK for "re-clocking" no dice.
As I want to keep the choice of what goes between a standard IIS input and the circuit above open, the circuit can be configured as clock master for 32X FS or 16X FS BCK. It can also be configured as re-clocker working on a divided MCK (/2/4/8) to reclock simultaneous outputs from FPGA's or CPLD's designed correctly (no stopped clock please). Makes it very messy. In reality I'll put 0402 resistor footprints and thus a solder bubble easily selects. Default stuffing obviously for 32X FS IIS, as this what we can guarantee.
Power supply, Supercapacitors again. I need to add a power supervisor IC, note to self.
Oh and before anyone b!tches about the "noisy TL431" and the "noisy 317" please fully understand and analyse the circuit, so you can understand what it does.
Thor
PS, not sure if I need to explain Hyloidealism. It essentially unifies idealism and materialism. It means we treat certain ideals, that have not been substantiated sufficiently to be classed as confirmed from am materialistic (objectivistic) view, but treat them as if they are actually real anyway and act accordingly. If you look at the circuit and read the comments, the ideals embodied here should be obvious.
Anyone else, please go and listen to your latest CMOS mega-oversampled and ASRC'ed etc. DAC that to some sound like a "Woke in a Gamelan" or "Hilarious Dummy Sound". This is not for you.
Despite lots of interesting content this thread is perilously closed to being closed by moderation. Keep the discussion respectful or the thread will be closed and deleted. Last warning.
SOT-89-3 AZ431AR-ATRE1, can be used, no need for TH, they have the same coeficient. And i see no issue in using it, many a circuit's have achieved over 130db with it in it. Tda1541a inherent noise is ~16uV, and this supply noise will be about x1000 less than the noise of the chip itself, so i'm down with it. We can make a three pin close to chip for the ones that would like to go that route.
Yes, with the right layout that will be fine. Just SOT-23 is no go.
Optimum self noise with most 431 is ~20uV. But the 431 are in effect used as DC servo. For AC the 1k & 100uF feedback loop leads to a 1.6Hz turnover. The output impedance is 33R, which limits current and in effect acts as series resistor for a lowpass into 25F/~10mOhm. which give sub mHz turnover and 431 noise reduced by ~70dB.
Yes, that works fine.
Thor
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