Even that is not absolutely true. That is because of the way CMOS IC's work (ground/supply bounce, lead frame impedance et al).
At best it is true in a first order approximation. A jittered BCK, WCK and DATA can still cause observable fidelity impairment at the output that materially degrade DAC IC performance.
But to each their own. Who am I to challenge false beliefs, plus it's wildly Off Topic as for the TDA1541 there isn't even such a thing as MCK.
Thor
So already one full page of completely unconstructive Bakwaas. My, my... So many snowflakes incapable to simple ignore dissenting views and get on with their own stuff.
What The Fudge? Bakwaas Band Kar!
How about some precision clocking?
To those who know it all, I know you do. I know you know better, can do better and it's all wrong. Thank you for keeping your comments to yourself.
If you look at the schematic and don't understand what it does either in context of a DAC or specifically... Take an EE evening course, or just accept it's "Big Magic", don't ask. There is such a thing as a stupid question (stupid answers too of course).
Intelligent questions welcome.
Thor
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I was hoping for a decent thread on a group design of a TDA1541 NOS DAC, but this is not going well.
@ThorstenL, can you at least try to not use Thors Hammer in every single post?
That's not really meant to be that. It is not a "group" design in the sense we discuss how it's going to be and then do it. I an not interested. Plus, if we do that we end up with something unmanageable that will never work.
It means to be about the REALISATION of a specific concept, that combines a lot of lessons learned and understanding gained all across the community.
I am not interested in re-debating and re-discussing previously covered territory.
It is a group realisation, not a group design. It's simple. I set out terms of reference.
If you agree with the whole thing, you join, if not, well there is that.
If you are not sure, as sensible questions that will allow you to decide if you agree and want to join in or not.
All else, well...
I expected worse.
I CAN. But after the start of this I am notably disinclined. I have neither time nor inclination to entertain trolls, fools, freeloaders and know-it-alls.
I would have done this in PM's but it seems impossible to have a group for PM on this site. And I'm happy to have things in the open.
Thor
Because it's pointless? It doesn't improve anything. Been tested by ECDesigns, lcsaszar and others.
Of course not, that's pointless. It's mostly magical thinking even in CMOS based IC's.
And the TDA1541 doesn't work the way CMOS IC's work. All that stopped clock stuff is pointless here. What matters is to have the slowest bit and word clocks and edges possible that leave an operational system at the required sample rates (also works for CMOS IC's, incidentally).
This is thanks to planar PNP input transistors in the TDA1541 digital input pin's being made with the base being a large capacitance into the substrate and the output switch transistors and diode connected transistors having their collectors being large planar structures with large capacitance (X 16) to the outputs.
In other words, your digital input pins on the TDA1541 are capacitor coupled to the output, with sufficient capacitance (~ 12pF per pin) to pass fast edges through to the output nearly unimpeded and of course all around the IC.
If you stop clocks you have to run BCK faster, this means you get more interference in less time. It is better to slow the clocks so we can slow the edges so that feed trough levels are minimal, at which point stopping the faster clock is worse than a slower continuous clock.
Thor
I'm gone. Can't do with self opinionated people who have the cheek to ask for collaboration and then shoot down every suggestion if it doesn't align with theirs.
I think it's not a discussion/suggestion thread but rather a how-to-materialize a specific circuit that Thorsten has in mind after the discussion have been done in the other threads. Since it's not gonna be run-of-mill do-it-like-all-the-others, the ones that assigned to it better know a thing or two about the layout of digital circuits in theory and practice. And of course there is work for the pcbs to be made and be tested.
I'm also sceptical about super capacitor based psu but I'm not gonna tear my shirt apart in anger and also it might be that the designer has some reasons behind this decision.
I wish I could do the surgery but I'm afraid the patient is not gonna like it.
I'm also sceptical about super capacitor based psu but I'm not gonna tear my shirt apart in anger and also it might be that the designer has some reasons behind this decision.
I wish I could do the surgery but I'm afraid the patient is not gonna like it.
I do actually have reasons.
Supercapacitors have come a long way. Modern low impedance ones, well, the ones I use are 25F 10mOhm 2.7V.
Another way of writing this is 25,000,000uF.
Self noise in Super Capacitors is extremely low, it is MOSTLY related to.ESR and adds a little ELF shot noise. Mechanical noise (microphonics) are equally.
The 1LF corner for a 25F/10mOhm super Capacitor is ~ 0.6Hz. at the HF end the corner frequency is around 60kHz.
A capacitor with 8S 2P is 6.25F/21.6V with 40mOhm ESR.
An RLC filter with two 1mH/2Ohm inductors and this capacitor bank has a PSRR of 40dB completely passive, from ~1Hz up to the LR corner at ~ 3Hz. At 30Hz we already have any noise from the source attenuated by 60dB and by 300Hz 80dB, 100dB at 3kHz.
As I will use normal 3-pin regulators before the RLC filter, we are looking at < 100uV wideband noise, largely flat in spectrum, with SMD LF rise, relating to the bandgap noise.
If we take a 300Hz bandwidth in this bandwidth we see likely << 10uV noise, which we attenuate by 40-80dB.
That means any noise in this circuit needs to be stated in nV (not per squareroot Hz but absolute).
It will be extremely hard to make any purely active regulator to come even close.
Of course, a supercapacitor based power supply needs several minutes to ramp up. Not acceptable in a commercial product. Of course, there are workarounds.
But for an "Ultimo Ratio" TDA1541 DAC I cannot think of anything that would perform better or that I would rather use.
No need to agree with me. Mind you. But that's my reasoning. A fundamentally passive power supply with a constant low impedance from 1Hz to > 50kHz and feck all noise. At least to me that rocks.
I of course subscribe to:
Not sure about the touch of genius here (probably not), but my courage is complete.
I miss the old geezer. And I start to understand him now.
Here's to Jocko!
Thor
Thorsten, can you explain what the role of the "group" is (not)?
Have you ever seen the Amish raise a Barn? Or do you know the story "Stone Soup"? Same thing.
We have a project. Someone is interested in the project and wants to see it become reality. See what everyone can do.
As @rfbrw pointed out, I can do this alone. But more eyes and brains catch bugs much easier and often before fabbing a PCB.
I have no idea who is interested (maybe nobody) and what they can contribute. I'm just sitting here with my borrowed pot filled with water, some wood I collected to make a fire and my amazing soup stone...
Thor
As said, i'm down for pcb design contribution. So it will be at least a participation on that field. And it will be populated, tested before release.
Not surprised.
The "coalition of those willing"?
The DAC design I propose. A lot of the reasons, tech etc. was debated elsewhere, peeps expressed interest in doing something with the understanding, ideas, concepts etc.
This is "doing something" thread. For those who do stuff, not endless talkers about the whichness of the why.
Thank you for your time.
Thor
Those who do stuff , have it done already , they do first and then come here to talk about it , you are the endless talker who fill thread for month with NO build at the end ........
you may not know it , but experiences comes with fact , you must do and failed if you want to learn , dont worry even if your schematics doesnt work nobody will laught at you , we are gentleman's here 😎
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The thread starts with a clear set of terms of reference. So thank you to everyone who reads the terms of reference and then decides to quiet leave or stay and see how it goes.
Those who do not read them will be disappointed and fools will not be suffered gladly.
If that offends, remember offense is taken, not given. I'd say sorry, but I'm not going to lie and I'm not.
At this point the whole thread has a SNR of -20dB (meaning there is ten times as much pointless noise as there is signal). That's terrible.
Thor