Hmmm...
I see this conversation mostly concerning heat dissipation, which of course is a very valid concern, but what of "sweet spot" tuning as a deciding factor for the bias?
I see this conversation mostly concerning heat dissipation, which of course is a very valid concern, but what of "sweet spot" tuning as a deciding factor for the bias?
I tried 800mV and briefly, 1V across the resistors. That would be 1.7A and ~2.1A bias.
The transistors were fine (under 80 degrees at the case and 65 degrees on the sink) because my heatsink was over-rated, but the resistors got really hot, as you might expect. Even though the power dissipation was within their limits, at one point I was measuring over 100 degrees on the little heatsink I had over them.
I remember the 1.7A bias point sounding extremely good, but I feared for long-term thermal stability (no thermistors in my F5!) so I backed it down to the recommended values after a couple of days of fooling about.
My heatsinks get up to about 50 degrees at this level of bias, and the devices are about 60-62 degrees (measured on the drain lead or the little bit of the tab at the top of the case).
The transistors were fine (under 80 degrees at the case and 65 degrees on the sink) because my heatsink was over-rated, but the resistors got really hot, as you might expect. Even though the power dissipation was within their limits, at one point I was measuring over 100 degrees on the little heatsink I had over them.
I remember the 1.7A bias point sounding extremely good, but I feared for long-term thermal stability (no thermistors in my F5!) so I backed it down to the recommended values after a couple of days of fooling about.
My heatsinks get up to about 50 degrees at this level of bias, and the devices are about 60-62 degrees (measured on the drain lead or the little bit of the tab at the top of the case).
You can first lower rail voltage to +/-16V, then increase bias to 1.8A or 2A. You also need to change the source resistors to 0R22 (just use 2x 0R47 in parallel to start with).
If you like the sound as is, then you can get the optimum R_load back to 6R and power up to 48W by going balanced. Rest see the balanced F5 thread.
Distortion reduces with bias current. Please read Nelson's paper.
Patrick
If you like the sound as is, then you can get the optimum R_load back to 6R and power up to 48W by going balanced. Rest see the balanced F5 thread.
Distortion reduces with bias current. Please read Nelson's paper.
Patrick
Here's another question:
The uninsulated package of TO-247 devices is connected to pin 2. In the F5, this means that the backs of both output devices are at the same potential, and further, that they are really directed connected through the PCB. Can I get away with mounting them on the same heatsink with no electrical insulation? Three things I can think of that are of concern are:
a) Electrocution, although the sink will never be at more than +-18~ volts, and there's current limiting. I'm working out chassis design to prevent accidental contact.
b) capacitance from having 1.5kilo's of steel sitting on the output
c) Will the extra path between the two MOSFET's mess things up
All in the pursuit of higher bias for my 6ohm speakers.
The uninsulated package of TO-247 devices is connected to pin 2. In the F5, this means that the backs of both output devices are at the same potential, and further, that they are really directed connected through the PCB. Can I get away with mounting them on the same heatsink with no electrical insulation? Three things I can think of that are of concern are:
a) Electrocution, although the sink will never be at more than +-18~ volts, and there's current limiting. I'm working out chassis design to prevent accidental contact.
b) capacitance from having 1.5kilo's of steel sitting on the output
c) Will the extra path between the two MOSFET's mess things up
All in the pursuit of higher bias for my 6ohm speakers.
The F5 uses a Pchannel connected to the positive supply and an Nchannel connected to the negative supply.
The two drains of these devices are almost the full rail to rail voltage apart. You must electrically isolate (insulate) the backs of the To247 from the common heatsink.
The two drains of these devices are almost the full rail to rail voltage apart. You must electrically isolate (insulate) the backs of the To247 from the common heatsink.
Pin 2 on each device are directly connected to each other over the PCB anyway, the heatsink is just going to be in parallel with this.
Are you saying insulation is necessary for the safety of it? The heatsink won't be exposed from the outside of the chassis.
Are you saying insulation is necessary for the safety of it? The heatsink won't be exposed from the outside of the chassis.
I Mean, the gain in thermal performance is substantial, I think. The Drain pad of the pakage theoritically is the same as pin 2. The only argument I see is the voltage potential on the exposed Heat Sink...
The F5 has 2 mosFETs.
A Pchannel connecting +ve supply to output and an Nchannel connecting -ve supply to output.
Am I correct or have I gone doo lally?
A Pchannel connecting +ve supply to output and an Nchannel connecting -ve supply to output.
Am I correct or have I gone doo lally?
So some actual measured data to help the discussion.
My F5X (balanced) uses 2SK1530 / 2SJ201. Each FET dissipates 32W.
Using Kerafol 82/86 insulator foil (you can buy those here in the commercial section of the forum, and not from me), the temperature difference between MOSFET case and the heatsink immediately next to it is 3°C. Using mica & grease, I get with the same setup somewhere around 10~12°C.
So the insulator, while important, is certainly not the deciding factor, that is if you use modern, high performance ones.
I stick to my opinion in post #15. The single parameter that is most limiting and that you cannot do anything about (except using more FETs in parallel, at the expense of increased capacitance) is the intrinsic Rthjc of the device.
Patrick
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My F5X (balanced) uses 2SK1530 / 2SJ201. Each FET dissipates 32W.
Using Kerafol 82/86 insulator foil (you can buy those here in the commercial section of the forum, and not from me), the temperature difference between MOSFET case and the heatsink immediately next to it is 3°C. Using mica & grease, I get with the same setup somewhere around 10~12°C.
So the insulator, while important, is certainly not the deciding factor, that is if you use modern, high performance ones.
I stick to my opinion in post #15. The single parameter that is most limiting and that you cannot do anything about (except using more FETs in parallel, at the expense of increased capacitance) is the intrinsic Rthjc of the device.
Patrick
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Does mica come in more than one thickness? I ordered mine from ebay. Maybe I can peel them apart if it makes a big temperature difference.
Yes, it varies from 0.05 to 0.2mm or so. My mica was 0.15-0.2mm bought on ebay and I peeled them to get 0.05
If you can get mica down to 1mil = 1thou = 0.001inch ~= 0.025mm then you will get excellent thermal performance. But check your mica is not split nor cracked. A split without thermal compound is another high thermal resistance interface.
Any rigid insulator, like mica, or aluminium oxide, would need thermal compound (such as thermal grease) on both sides (one towards heatsink and once towards the active device). Even if you could reduce the insulator thickness to zero, the thermal resistance is still limited by those 2 layers of thermal compound.
This is where Kerafol scores. As a compliant foil, it does not need those 2 layers of thermal compound.
Patrick
This is where Kerafol scores. As a compliant foil, it does not need those 2 layers of thermal compound.
Patrick
A properly assembled thermal compound interface is a metal to metal interface.
The gaps left in scratches, hollows, roughnesses, etc., are filled to ensure no air is present in the interface.
This metal to metal interface is the best we can obtain in a mechanical fixing.
I accept that mica with two interfaces must be worse than this, but done properly there is total exclusion of air from the thermal flow route.
Does a conformal pad significantly interfere with the thermal resistance of the metal to metal interface? It cannot be better, but is it worse?
Yes, the best of the conformal pads have data showing improved performance over very thin mica.
The vast majority of conformal pads on the market are considerably worse than very thin mica.
I think we are looking at degrees of worsening, i.e. increasing thermal resistance.
The gaps left in scratches, hollows, roughnesses, etc., are filled to ensure no air is present in the interface.
This metal to metal interface is the best we can obtain in a mechanical fixing.
I accept that mica with two interfaces must be worse than this, but done properly there is total exclusion of air from the thermal flow route.
Does a conformal pad significantly interfere with the thermal resistance of the metal to metal interface? It cannot be better, but is it worse?
Yes, the best of the conformal pads have data showing improved performance over very thin mica.
The vast majority of conformal pads on the market are considerably worse than very thin mica.
I think we are looking at degrees of worsening, i.e. increasing thermal resistance.
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