Hi @gentlevoice,
I haven't read the thread, but each time I needed to uses vias linning layout I finished each time with avoiding it and prefered to make traces further appart from each others avoiding also ground poors island the much I can and stray capacitance with coplanar wave guides... I eventually apply guard rings, although in some soft (Kicad) I had problem not being made by the pcb maker to have the silk screen removed on it in order it is effective to guard !
Sorry, certainly too much simple answer !
Hey I enjoy a lot the little capacitance and inductance kit you advised me one year or two ago 🙂
cheers, hope your DAC project is going on 😎
I haven't read the thread, but each time I needed to uses vias linning layout I finished each time with avoiding it and prefered to make traces further appart from each others avoiding also ground poors island the much I can and stray capacitance with coplanar wave guides... I eventually apply guard rings, although in some soft (Kicad) I had problem not being made by the pcb maker to have the silk screen removed on it in order it is effective to guard !
Sorry, certainly too much simple answer !
Hey I enjoy a lot the little capacitance and inductance kit you advised me one year or two ago 🙂
cheers, hope your DAC project is going on 😎
Last edited:
Regarding via spacing for a shield fence:
PCB guidelines should be based on the wavelength, λ at fMAX
Via spacing should be << λ/10 when connecting for board-level-shields to a guard trace or building a perimeter via fence, per graphic above.
Ideally, this means via spacing of λ/50.
So determine fmax for your design and use the wavelength calculator in Saturn PCB. You should update to the latest version
PCB guidelines should be based on the wavelength, λ at fMAX
Via spacing should be << λ/10 when connecting for board-level-shields to a guard trace or building a perimeter via fence, per graphic above.
Ideally, this means via spacing of λ/50.
So determine fmax for your design and use the wavelength calculator in Saturn PCB. You should update to the latest version
The folks at Altium Academy has several good videos on vias: https://www.youtube.com/@AltiumAcademy
They focus primarily on RF and fast digital circuits, it seems, so perhaps the content is applicable here.
Tom
They focus primarily on RF and fast digital circuits, it seems, so perhaps the content is applicable here.
Tom
Stubs will radiate at frequencies at λ/4, λ3/4 and so on for all the λn/4 where n is an odd integer – however, the main radiation occurs at λ/4
Again, use Saturn to find the length of the via/stub and then calculate the frequency of radiation.
Again, use Saturn to find the length of the via/stub and then calculate the frequency of radiation.
Hi all,
Thanks for considering & replying 😉 ...
@Markw4: You have PM.
@diyiggy: Well, I think there are really many different approaches to PCB layout - not least depending on what one wishes to achieve. And regarding via stitching or via fences it seems to me that one of the challenges is that if they are not used correctly they may actually cause more trouble than they solve (you may already know this). The same apparently is the case for coplanar wave guides - so "as usual with audio" (? 🙄 ?) IME things rarely are straightforward ... Anyway, pleased to hear that you can use Saturn's PCB help - Kudos passed on to the creators of the software!
@VivaVee: Thanks again for considering my questions which make me think that I may have been imprecise in my wording of my questions - but maybe you have actually replied already ... Regarding the distance between the vias what I was thinking about was at which frequency the now "swiss cheese" PCB would stop function as a shield. But maybe this is found by calculating the distance between the vias relative to the lambda of the maximum frequency involved as you described in #42?
Regarding the stubs it is good to know about the frequencies involved, thanks ... Any chance you would also know about the radiation level, i.e. how much these vias radiate as a function of distance to the "receiving trace"? ... has made me think of buried & hidden vias - would be nice to have
@tomchr: ... thank you also for chiming in, Tom 😉 ...
And, yes, Altium is a very relevant site in this context I would say. Only IMHO it can be a bit challenging to find specific information I may be looking for due to the wealth of information on the site and also on their youtube channel (I guess you may know of this in other contexts?). But I suppose this is somehow a luxury problem ... and following your link this morning I did find pieces of information that further helps assemble the PCB layout puzzle
Thanks again for replying - & best wishes for your day!
Jesper
Thanks for considering & replying 😉 ...
@Markw4: You have PM.
@diyiggy: Well, I think there are really many different approaches to PCB layout - not least depending on what one wishes to achieve. And regarding via stitching or via fences it seems to me that one of the challenges is that if they are not used correctly they may actually cause more trouble than they solve (you may already know this). The same apparently is the case for coplanar wave guides - so "as usual with audio" (? 🙄 ?) IME things rarely are straightforward ... Anyway, pleased to hear that you can use Saturn's PCB help - Kudos passed on to the creators of the software!
@VivaVee: Thanks again for considering my questions which make me think that I may have been imprecise in my wording of my questions - but maybe you have actually replied already ... Regarding the distance between the vias what I was thinking about was at which frequency the now "swiss cheese" PCB would stop function as a shield. But maybe this is found by calculating the distance between the vias relative to the lambda of the maximum frequency involved as you described in #42?
Regarding the stubs it is good to know about the frequencies involved, thanks ... Any chance you would also know about the radiation level, i.e. how much these vias radiate as a function of distance to the "receiving trace"? ... has made me think of buried & hidden vias - would be nice to have
@tomchr: ... thank you also for chiming in, Tom 😉 ...
And, yes, Altium is a very relevant site in this context I would say. Only IMHO it can be a bit challenging to find specific information I may be looking for due to the wealth of information on the site and also on their youtube channel (I guess you may know of this in other contexts?). But I suppose this is somehow a luxury problem ... and following your link this morning I did find pieces of information that further helps assemble the PCB layout puzzle
Thanks again for replying - & best wishes for your day!
Jesper
Yup, for sure Jesper. As I do not use the complex software suits, I try to think Ott's EMC strategy but when it seems to be counterproductive for audio where we don't deal at Ghz speeds. So:
- I open the ref layers a little to avoid couplings (stray capacitance, antennas as much one can, isolation of current loops) relaxing the plain ground layer mantra of filling at max.
- I cope to simple strategy for the DACs pcb with 5 to 7 mm vias stitching between Ref layer and the top ground pours I try to avoid though- i.e. when too much little or long ground poors or isolated pours between // traces or to isolate two or more high speed traces (clock, I2S...), I prefer spacing and use only the 5 mil bottom Ref layer distance to adapt impedance of those digital traces, so no coplanar WG entering in the impedance calculation. Here I see more the vias as antenna than isolators... I prefer distance isolation so, and open the Ref to isolate different current return paths and ground loops from each others. If guarding I do not use vias fence stitching but if really away from signals, i.e. more to isolate parts of the pcb, pcb outline, etc)
- I space top ground layer if present 5 mm away from high speed op amps for stray capacitance free (bye bye Ott EMC here, i.e. I open also the Ref layer but less ,2 mm; i.e. I prefer the ground loop of the signal to be a little larger in spite of the signal traces and pads are stray capacitance contaminated by the signal return path but also isolate as much as possible the power supply return paths from the signals' (but anyway they met at op amps output with the close power decouplings, so I try to decouple closer to the output of the amps with tigther distances between the small and the bigger decoupling cap and the output pins of the op amp). Here also the PS traces impedance is a pain, and isolated return paths are tempting, but anyway I focuse more on inductance with them.
I cross the fingers not to be too much away than what needed hopping that works, ahaha, your picture of puzzle is a good one I find 🙂! Me I sacrifice a chicken, as it's a little black art when not being Highspeed Electrical engineer - hey your remember the cool Marce member 🙂 (and our needs are not so high speed but for the digital feeding/clock)
Sometime it is a pain... when having several digital ICs chips like single output channel ones ! And also with single dac chips with the recent discussion about he current return paths and analog/digital ground of the TDA1541A by T. Loesch - the long thread-.
Best
- I open the ref layers a little to avoid couplings (stray capacitance, antennas as much one can, isolation of current loops) relaxing the plain ground layer mantra of filling at max.
- I cope to simple strategy for the DACs pcb with 5 to 7 mm vias stitching between Ref layer and the top ground pours I try to avoid though- i.e. when too much little or long ground poors or isolated pours between // traces or to isolate two or more high speed traces (clock, I2S...), I prefer spacing and use only the 5 mil bottom Ref layer distance to adapt impedance of those digital traces, so no coplanar WG entering in the impedance calculation. Here I see more the vias as antenna than isolators... I prefer distance isolation so, and open the Ref to isolate different current return paths and ground loops from each others. If guarding I do not use vias fence stitching but if really away from signals, i.e. more to isolate parts of the pcb, pcb outline, etc)
- I space top ground layer if present 5 mm away from high speed op amps for stray capacitance free (bye bye Ott EMC here, i.e. I open also the Ref layer but less ,2 mm; i.e. I prefer the ground loop of the signal to be a little larger in spite of the signal traces and pads are stray capacitance contaminated by the signal return path but also isolate as much as possible the power supply return paths from the signals' (but anyway they met at op amps output with the close power decouplings, so I try to decouple closer to the output of the amps with tigther distances between the small and the bigger decoupling cap and the output pins of the op amp). Here also the PS traces impedance is a pain, and isolated return paths are tempting, but anyway I focuse more on inductance with them.
I cross the fingers not to be too much away than what needed hopping that works, ahaha, your picture of puzzle is a good one I find 🙂! Me I sacrifice a chicken, as it's a little black art when not being Highspeed Electrical engineer - hey your remember the cool Marce member 🙂 (and our needs are not so high speed but for the digital feeding/clock)
Sometime it is a pain... when having several digital ICs chips like single output channel ones ! And also with single dac chips with the recent discussion about he current return paths and analog/digital ground of the TDA1541A by T. Loesch - the long thread-.
Best
Last edited:
1. Yes, use the #42 description@VivaVee: Thanks again for considering my questions which make me think that I may have been imprecise in my wording of my questions - but maybe you have actually replied already ... Regarding the distance between the vias what I was thinking about was at which frequency the now "swiss cheese" PCB would stop function as a shield. But maybe this is found by calculating the distance between the vias relative to the lambda of the maximum frequency involved as you described in #42?
Regarding the stubs it is good to know about the frequencies involved, thanks ... Any chance you would also know about the radiation level, i.e. how much these vias radiate as a function of distance to the "receiving trace"? ... has made me think of buried & hidden vias - would be nice to have
2. Radiated power is specific to your application - both parts and layout. And then you would need a 3D EM field solver. So in your case, follow good design practice (keep stubs short and nonexistent where possible) and then ignore or pray, which ever best leaves you able to sleep easily
And lastly, please use a solid reference/ground plane. Star grounding was all the rage in the 1970s but in the EM rich environment of the modern world it is something for the history books. Unfortunately, the internet allows easy access to outdated advice. And ChatGPT creates a superb echo chamber for nonsense. OK, rant mode, off 🙂
hi diyggy,
In the ASR forum, I've been asked "not to tell" that in PCBs for audio any speeds matters. Weird to me but... 🙂 funny.
In ASR, what matters are "audio" frequencies, thus above 22kHz, it's all about psycho effect 🙂 (what a jerk guru..)
So, to you, in audio, what's the highest frequency on PCBs that has a effect on the SQ ?
Not sure I understand the question. But at ASR they are using DACs, no ? Short answer: with clocks, high speed op amp, digital traces, etc ! It is high frequencies domain and the pcb has to be disigned accordingly. So yes, what happen above the audio range matters and can be heard.
What I meant : it was not a 5 Ghz smartphone design where the pcb is more difficult. But it is still difficult. A not well made pcb for DAC purpose (I think it is the topic) needs then some strategies in the layout, the higher speeds the more difficult. So for some RF EE, ou DAC is still low speeds, ahaha ! But it is still sensible and can be heard (do you remember jitter things for illustration 😉 )
related to the discussion star grounding strategy can be used for old low speed DAC clocks with standalone dac chip ic for some reason. This strategy is more difficult to design but can be productive as well for figthing pollution purpose as well as not mixing some currents and avoid some crosstalks. They can use solid pours in the same pcb. I have a DAC designed that way by an audio company but it is a "low speed" TDA1541A ! Sounds fine.
Nowadays with higer speed clock (100 M hz is seen) and modern DAC chips, or very fast op amps (some use op amps above the Ghz bandwidth) because of the RF, the layout is more difficult (EMC/EMI, still mixed signal environment) If not well made, yes it can be heard in the audio range. It is not only the limit of the clock speed or the embeded that matter only, it is also the EMI polution made by suroundings electro magnetics waves the pcb can be victim (air and solid : powersupplies around, wifi, led equipment, microwave oven, blutooth 4G/5G, etc). Not the same frquency affects the same things (digital,powersupplies) , also in the analog domain,, amplifiers works at two or three digit M hz range, an oscillation can be heard in the said audio range, etc. And because it is high speed it makes sense too to design the pcb and the device to be safe to protect the other devices around (EMC... input from ViaVee above)
Hope I answered to your question.
What I meant : it was not a 5 Ghz smartphone design where the pcb is more difficult. But it is still difficult. A not well made pcb for DAC purpose (I think it is the topic) needs then some strategies in the layout, the higher speeds the more difficult. So for some RF EE, ou DAC is still low speeds, ahaha ! But it is still sensible and can be heard (do you remember jitter things for illustration 😉 )
related to the discussion star grounding strategy can be used for old low speed DAC clocks with standalone dac chip ic for some reason. This strategy is more difficult to design but can be productive as well for figthing pollution purpose as well as not mixing some currents and avoid some crosstalks. They can use solid pours in the same pcb. I have a DAC designed that way by an audio company but it is a "low speed" TDA1541A ! Sounds fine.
Nowadays with higer speed clock (100 M hz is seen) and modern DAC chips, or very fast op amps (some use op amps above the Ghz bandwidth) because of the RF, the layout is more difficult (EMC/EMI, still mixed signal environment) If not well made, yes it can be heard in the audio range. It is not only the limit of the clock speed or the embeded that matter only, it is also the EMI polution made by suroundings electro magnetics waves the pcb can be victim (air and solid : powersupplies around, wifi, led equipment, microwave oven, blutooth 4G/5G, etc). Not the same frquency affects the same things (digital,powersupplies) , also in the analog domain,, amplifiers works at two or three digit M hz range, an oscillation can be heard in the said audio range, etc. And because it is high speed it makes sense too to design the pcb and the device to be safe to protect the other devices around (EMC... input from ViaVee above)
Hope I answered to your question.
Last edited:
@VivaVee: Thanks again for clarifying 😉 ...
I think what I will do in this design - since it is very sensitive to noise - is to entirely eliminate signal through-vias that are not related to the important signals. It should be possible and feasible. And no worries - I would not use star grounding in the circuitry I am designing right now where rise times are at 0.3ns ... It might be made to work but likely EMI & many other real troubles would emerge
...
And about ChatGPT ... having experienced a couple of times that its replies has been quite incorrect I am now in "careful observation mode" so to speak ... Hopefully it will improve over time as I think it would be a tremendous tool to have available (together with ~2.5 million big size wind turbines to power it).
Cheers, Jesper
I think what I will do in this design - since it is very sensitive to noise - is to entirely eliminate signal through-vias that are not related to the important signals. It should be possible and feasible. And no worries - I would not use star grounding in the circuitry I am designing right now where rise times are at 0.3ns ... It might be made to work but likely EMI & many other real troubles would emerge
...And about ChatGPT ... having experienced a couple of times that its replies has been quite incorrect I am now in "careful observation mode" so to speak ... Hopefully it will improve over time as I think it would be a tremendous tool to have available (together with ~2.5 million big size wind turbines to power it).
Cheers, Jesper
I wonder about the via wall related to the other layers. When used on the middle of the pcb (opposed to the pcb edges I mean) does the clearance between vias stubs on the under layers not a problem and create bigger ground loops for the currents flowing on those under layers ?
Plus I wonder if the clearances around the stubes on those layers are not counterproductive for EMI, creating local antennas ?
Most of the time because the price or the printer we do not use blind or burried vias, so those striplines for diy are most of the time full through vias that go from the top layer to the bottom one.
Am I too much worried and vias fencing for RF spead figthing or isolation is a better practice than making the PCB a littlee higher in order to make the traces farer ? But the bigger the board the less good for EMI and figthing against that acording the Sierra paper linked above by gentlevoice fellow ?
Is the signal integrity could be impacted by using too much of these striplines ?
Plus I wonder if the clearances around the stubes on those layers are not counterproductive for EMI, creating local antennas ?
Most of the time because the price or the printer we do not use blind or burried vias, so those striplines for diy are most of the time full through vias that go from the top layer to the bottom one.
Am I too much worried and vias fencing for RF spead figthing or isolation is a better practice than making the PCB a littlee higher in order to make the traces farer ? But the bigger the board the less good for EMI and figthing against that acording the Sierra paper linked above by gentlevoice fellow ?
Is the signal integrity could be impacted by using too much of these striplines ?
This thread got me thinking of what I did to manage impedance discontinuities when I was designing microwave PCBs. I didn't remember it be especially tedious or labor intensive. Then I realized why: We had software to analyse the routing & trace layout built into our PCB CAD tool. The tool output would be included in the PCB design review to make sure any issues got fixed.
If there is a low cost or free version of that out there on the web, I'd highly recommend using it, despite an ardous learning curve. (Complex problems create complex tools.) It can be calculated by hand, but it does require amazing amounts of effort.
Hi Philbo King:
Hmmm ... yups it is also my wish to find a (reasonably) free simulator that could work with these simulations, however, apart from openEMS I do not know of such softwares. Unfortunately I am not a programmer either and since openEMS appears to depend on either Matlab or Python scripts I have decided to not try it out. In the meantime I tend to rely on the coplanar wave guide section of Saturn's PCB toolkit - which actually in most instances match the use-cases I work with. But it would indeed be nice to have a more capable simulator - in due time, hopefully
Cheers, Jesper
Hmmm ... yups it is also my wish to find a (reasonably) free simulator that could work with these simulations, however, apart from openEMS I do not know of such softwares. Unfortunately I am not a programmer either and since openEMS appears to depend on either Matlab or Python scripts I have decided to not try it out. In the meantime I tend to rely on the coplanar wave guide section of Saturn's PCB toolkit - which actually in most instances match the use-cases I work with. But it would indeed be nice to have a more capable simulator - in due time, hopefully
Cheers, Jesper
You might care to try https://www.elmerfem.org/blog/ which has a GUI interface rather than the scripting/programming interface taht everything else seems to use.
I have no experience with this as I have access to solvers that link to the physical pcb construct as well as picking up IBIS models for any active devices. But that way be $$$.
I have no experience with this as I have access to solvers that link to the physical pcb construct as well as picking up IBIS models for any active devices. But that way be $$$.
No. Board size is not relevant. There is so much else that can go right or wrong before the board size is relevant.
Can you point to where in that document you found that reference?
@VivaVee:
Thanks for the tip ... I have taken a look at it this morning but also having checked out the Elmer discussion forum my feel (not necessarily correct, I admit) is that it may just be something that could take quite a bit of time to learn to use (and might also have errors here and there). So at this point in time I will keep it in mind but will not for now go any further with it.
And then maybe at some point in time there will be funds to invest in one of the commercial softwares
Cheers, Jesper
Thanks for the tip ... I have taken a look at it this morning but also having checked out the Elmer discussion forum my feel (not necessarily correct, I admit) is that it may just be something that could take quite a bit of time to learn to use (and might also have errors here and there). So at this point in time I will keep it in mind but will not for now go any further with it.
And then maybe at some point in time there will be funds to invest in one of the commercial softwares
Cheers, Jesper
The Sierra paper above? Ott ? The littliet the more EMI imune (A to B comparaisson), no? Or maybe smaller board is just the consequence of a more compact layout made for RF ?
I was referring to the Sierra paper.
Smaller passive components are generally better from an EMC perspective because of reduced package related parasitics.
Smaller active devices are often worse due to higher switching speeds and hence a wider noise bandwidth.
A larger PCB allows for a larger reference plane which allows components to be further from the edge which reduces edge radiation. But there are other ways to mitigate this.
So I prefer to stay away from sweeping generalisations...
Smaller passive components are generally better from an EMC perspective because of reduced package related parasitics.
Smaller active devices are often worse due to higher switching speeds and hence a wider noise bandwidth.
A larger PCB allows for a larger reference plane which allows components to be further from the edge which reduces edge radiation. But there are other ways to mitigate this.
So I prefer to stay away from sweeping generalisations...