Hi all,
I would appreciate a bit of insight into this, if anyone here knows:
1. Vias lining a PCB trace - impedance change: How do the GND connecting vias lining both sides of a PCB trace (digital traces in particular) change the impedance of the PCB trace? Since the electrical fields surrounding the PCB trace is altered when adding these GND connecting vias to each side of the PCB trace I would guess that it also alters the PCB trace impedance, however, I have not been able to find any mention of this anywhere ... ? Anyone knows about this (I would also much appreciate a link to a short text describing the optimum way of placing these vias, should one of you have such a link)?
An example of what I am thinking about can be found here:
https://electronics.stackexchange.com/questions/39834/placement-of-vias-to-connect-ground-planes
2. Crosstalk differences: Also, I have been wondering to what extent such vias alter the crosstalk between traces? ... Robert Feranec in one of his youtube videos (a trace radiation simulation without vias is shown from 15:13 - with vias from 16:03) illustrates how these lining vias greatly reduce the radiation from the trace - something that I reckon will also greatly reduce crosstalk:
However, when e.g. using the Saturn PCB toolkit (v. 7.11) the crosstalk numbers appear to be relatively high (and it is not described in the tool kit help whether or not lining vias are considered in the crosstalk calculations) ... That the Saturn crosstalk numbers appear to be high is my "assumption" as e.g. Analog Devices in their layout of the AD4630 EVM board's input traces according to the Saturn PCB toolkit would have a crosstalk coefficient between the two input channels of ~ -116 dB (1 MHz sine wave=~350 ns rise time, 10mm trace spacing, 10 mm trace coupling, trace-to-gnd plane distance 0.2mm, FR-4 board, signal voltage 5V). Which is quite high considering that this ADC is capable of a much lower noise floor. A link to the AD4630 EVM board - just FYI:
https://www.analog.com/en/design-ce...n-boards-kits/EVAL-AD4630-24.html#eb-overview
So I wonder how much lining vias - which are lining the AD4630 board's input traces and also discussed in the Feranec video - alters the radiation from a trace and thus also the trace's impedance?
BTW in searching for this information on Google I found an article on guard rings in microstrip & stripline PCBs. Quite interesting IMHO.
https://cdn.teledynelecroy.com/file...guard_traces_with_optimized_shorting_vias.pdf
If somebody here knows about the above if would appreciate your feedback.
Cheers & have a good day,
Jesper
I would appreciate a bit of insight into this, if anyone here knows:
1. Vias lining a PCB trace - impedance change: How do the GND connecting vias lining both sides of a PCB trace (digital traces in particular) change the impedance of the PCB trace? Since the electrical fields surrounding the PCB trace is altered when adding these GND connecting vias to each side of the PCB trace I would guess that it also alters the PCB trace impedance, however, I have not been able to find any mention of this anywhere ... ? Anyone knows about this (I would also much appreciate a link to a short text describing the optimum way of placing these vias, should one of you have such a link)?
An example of what I am thinking about can be found here:
https://electronics.stackexchange.com/questions/39834/placement-of-vias-to-connect-ground-planes
2. Crosstalk differences: Also, I have been wondering to what extent such vias alter the crosstalk between traces? ... Robert Feranec in one of his youtube videos (a trace radiation simulation without vias is shown from 15:13 - with vias from 16:03) illustrates how these lining vias greatly reduce the radiation from the trace - something that I reckon will also greatly reduce crosstalk:
However, when e.g. using the Saturn PCB toolkit (v. 7.11) the crosstalk numbers appear to be relatively high (and it is not described in the tool kit help whether or not lining vias are considered in the crosstalk calculations) ... That the Saturn crosstalk numbers appear to be high is my "assumption" as e.g. Analog Devices in their layout of the AD4630 EVM board's input traces according to the Saturn PCB toolkit would have a crosstalk coefficient between the two input channels of ~ -116 dB (1 MHz sine wave=~350 ns rise time, 10mm trace spacing, 10 mm trace coupling, trace-to-gnd plane distance 0.2mm, FR-4 board, signal voltage 5V). Which is quite high considering that this ADC is capable of a much lower noise floor. A link to the AD4630 EVM board - just FYI:
https://www.analog.com/en/design-ce...n-boards-kits/EVAL-AD4630-24.html#eb-overview
So I wonder how much lining vias - which are lining the AD4630 board's input traces and also discussed in the Feranec video - alters the radiation from a trace and thus also the trace's impedance?
BTW in searching for this information on Google I found an article on guard rings in microstrip & stripline PCBs. Quite interesting IMHO.
https://cdn.teledynelecroy.com/file...guard_traces_with_optimized_shorting_vias.pdf
If somebody here knows about the above if would appreciate your feedback.
Cheers & have a good day,
Jesper
Ground planes or copper pours are just a small part of getting a pcb right and hum free.
Star grounding is vital.
Also the power supply must be kept separate so you dont modulate audio ground with power supply smoothing cap charging impulses.
Keep high current and high VAC away from audio signals.
Try to keep transformers away from audio signal to stop cross coupling.
Its a case of getting it all right to get good results.
Star grounding is vital.
Also the power supply must be kept separate so you dont modulate audio ground with power supply smoothing cap charging impulses.
Keep high current and high VAC away from audio signals.
Try to keep transformers away from audio signal to stop cross coupling.
Its a case of getting it all right to get good results.
Hi Nigel ... thanks for considering & replying - but in this context I am specifically looking for more information about the effects of vias lining traces & crosstalk magnitudes particularly in relation to digital transmission.
Cheers, Jesper
Cheers, Jesper
I suspect vias dont make a big difference unless tiny.
I try to avoid vias if carrying a lot of current.
Depends on how thick the via tube is.
Routing the tracks away from other interfering tracks is more important.
I designed a USB scope and the results were 10KHz signal sat on top of wanted signal.
I had routed track beneath an TC7660 which has an internal 10KHz oscillator.
I also had 8MHz sat on the same signal.
I had run wanted signal next to microcontroller 8MHz crystal circuit.
Rookie mistakes of course but part of the learning curve.
I try to avoid vias if carrying a lot of current.
Depends on how thick the via tube is.
Routing the tracks away from other interfering tracks is more important.
I designed a USB scope and the results were 10KHz signal sat on top of wanted signal.
I had routed track beneath an TC7660 which has an internal 10KHz oscillator.
I also had 8MHz sat on the same signal.
I had run wanted signal next to microcontroller 8MHz crystal circuit.
Rookie mistakes of course but part of the learning curve.
Hi again, Nigel ...
I tend to agree with this but if you take a look e.g. at the Feranec video I linked to it can be seen that vias actually do make quite a difference. However, I - at least currently - do not have any tools to assess where to place the lining vias relative to the trace in question (the Saturn PCB toolkit to my knowledge does not have such a tool). Except for some general advice from e.g. Rick Hartley on placing the vias with a lambda/20 distance relative to the highest frequency found on the PCB (RF signal advice). So I would like to find out more about this ...
Hope you solved your USB scope challenge 😉
BR - Jesper
I tend to agree with this but if you take a look e.g. at the Feranec video I linked to it can be seen that vias actually do make quite a difference. However, I - at least currently - do not have any tools to assess where to place the lining vias relative to the trace in question (the Saturn PCB toolkit to my knowledge does not have such a tool). Except for some general advice from e.g. Rick Hartley on placing the vias with a lambda/20 distance relative to the highest frequency found on the PCB (RF signal advice). So I would like to find out more about this ...
Hope you solved your USB scope challenge 😉
BR - Jesper
Adding the vias will reduce the characteristic impedance: without them, the plane opposite to the track will be coupled through the inter-plane characteristic impedance. This impedance will be relatively low but not negligible, and it will have quirks because the planes aren't infinite and will return various reflections.
For a similar reason, the xtalk will be improved by the vias, because they will disable the plane/plane transmission line
For a similar reason, the xtalk will be improved by the vias, because they will disable the plane/plane transmission line
My guess would be that it lowers the impedance. This is taking me way back to when I first started in my career, working with high speed ECL, having sub-ns transition times. They'd build boards with adjacent traces, drive one trace and measure the crosstalk on the "victim" line, which of course would depend on the length or parallelism. This was all 50 Ohm stuff with formal termination resistors at the end of each line; I've never grasped how the transition was made to non-terminated controlled impedance etch used in all modern PC and server MBs... Those computers had a power supply rail just for the termination resistors.
I suppose transmission line impedance doesnt matter as long as the line length is, say, 10X shorter in propagation delay time compared to the transition time of the digital signal. Sub-ns worked out to be sub-ft; these were big mainframe computers where signal routing on the same PCB could be > 12 inches.
The tranny line model was described as an integral over an LC string; series L, shunt C. By putting a wall of grounded vias on each side of an etch line, I imagine that increases the value of the shunt C component.
I remember we had a layup calculator that would determine the impedance of an etch line. The input was a pattern of ascii characters using +, -, something like;
------------------------------
++++++++++++++++++
++++++++---++++++++
++++++++++++++++++
------------------------------
Which is how you'd represent an etch line between two ground planes; the + being FR4, the -, copper. Of course, I cant actually remember which characters represented what, but imagine developing or working with that.
They handed us this book to reference what we were working on: https://www.yumpu.com/en/document/read/18554002/mecl-system-design-handbook PCB design was Chapter 3. It should be illuminating on this topic.
Hi both ...
@Elvee: Thanks for your feedback & explanation - it makes good sense 😉 ... However - any chance you know of an article or a link where there is an accessible formula for the magnitude of the trace impedance change relative to the placement of vias? Would be great to know what the actual change is ...
@jjasniew: Thank you also for your reply & sharing a bit of your past 🙂 ...
In my understanding it is the signal rise time relative to the length of the transmission line that matters (I may be mistaken here, though). The higher the rise time the shorter the transmission line can be before impedance matching becomes important. And there are 1/4 lambda, 1/10 lambda and 1/20 lambda rules, but I reckon that these rules were originally conceived in computer signal integrity contexts and not necessarily directly applicable to audio related transmissions ... (?)
Thanks for the link to the book - looks comprehensive! yet quite hands-on in terms of practical advices ... I also did take a look at chapter 3, however, I cannot see that there is anything directly related to vias & via placement along a trace ... Might I have missed something?
Again - thanks both of you for your feedbacks 😉
Cheers,
Jesper
@Elvee: Thanks for your feedback & explanation - it makes good sense 😉 ... However - any chance you know of an article or a link where there is an accessible formula for the magnitude of the trace impedance change relative to the placement of vias? Would be great to know what the actual change is ...
@jjasniew: Thank you also for your reply & sharing a bit of your past 🙂 ...
In my understanding it is the signal rise time relative to the length of the transmission line that matters (I may be mistaken here, though). The higher the rise time the shorter the transmission line can be before impedance matching becomes important. And there are 1/4 lambda, 1/10 lambda and 1/20 lambda rules, but I reckon that these rules were originally conceived in computer signal integrity contexts and not necessarily directly applicable to audio related transmissions ... (?)
Thanks for the link to the book - looks comprehensive! yet quite hands-on in terms of practical advices ... I also did take a look at chapter 3, however, I cannot see that there is anything directly related to vias & via placement along a trace ... Might I have missed something?
Again - thanks both of you for your feedbacks 😉
Cheers,
Jesper
The number of parameters to take into account is huge: density of the vias, closeness to the track, PCB constants, etc.
You could use an online calculator to compare two situations.
First, compute the impedance for a single-sided case, then for the case where the strip and ground plane are on opposite sides (this one will be slightly higher). If you use a high enough density of vias, these impedances will be paralleled.
Without the vias, these impedances will be paralleled through the interplanes characterisic impedance, which will be quite low but very irregular due to the propagation/reflections at various frequencies, depending on the shape of the planes.
This is a good starting point, but it won't yield exact results: the method neglects fringe or proximity effects for example.
For a more accurate picture, you need to use specialized software, like EMworks or EMpro, but I don't know whether a free or demo version exists.
These softs are behemoth costing a fortune, totally out of reach of a DIYer
There is a concept called a 'via fence' that you may be thinking of. Please see the following link and the attached file: https://en.wikipedia.org/wiki/Via_fence
For audio electronics, the concepts seem most likely only applicable for higher harmonics of fast clock edge rise-times. Maybe that's one reason to moderate rise times to not faster than is optimal/sufficient for a particular dac implementation.
A google search for 'via fence' is likely to turn up additional info. If need be one can always PM to discuss how articles might be available directly from authors or through other resources.
For audio electronics, the concepts seem most likely only applicable for higher harmonics of fast clock edge rise-times. Maybe that's one reason to moderate rise times to not faster than is optimal/sufficient for a particular dac implementation.
A google search for 'via fence' is likely to turn up additional info. If need be one can always PM to discuss how articles might be available directly from authors or through other resources.
Last edited:
Hi both - & thank you for your fine feedbacks ...
@Elvee: Hmmm ... I think I would prefer to be quite precise in a calculation of the trace impedance change .. and so I checked out EMWorks & EMpro but as far as I can see they are beyond my means for this. A pity that something like Saturn does not have this feature - I reckon that for higher frequency designs it is almost imperative to know what the trace impedance changes are when adding vias ..
@Markw4: Thanks again for your feedback, Mark. I've looked into both of your links, however, I think that I am looking for something slightly different - maybe using a different term in English? I'm looking for more specific information about vias lining a trace as part of a copper pour (on the same plane) and then connecting to an underlying GND plane. Might you know what this may be called? I guess that when I first know what it is called there may be articles about it - just haven't found the right wording yet and then Google is less effective ...
Have a good day both of you 😉
Jesper
@Elvee: Hmmm ... I think I would prefer to be quite precise in a calculation of the trace impedance change .. and so I checked out EMWorks & EMpro but as far as I can see they are beyond my means for this. A pity that something like Saturn does not have this feature - I reckon that for higher frequency designs it is almost imperative to know what the trace impedance changes are when adding vias ..
@Markw4: Thanks again for your feedback, Mark. I've looked into both of your links, however, I think that I am looking for something slightly different - maybe using a different term in English? I'm looking for more specific information about vias lining a trace as part of a copper pour (on the same plane) and then connecting to an underlying GND plane. Might you know what this may be called? I guess that when I first know what it is called there may be articles about it - just haven't found the right wording yet and then Google is less effective ...
Have a good day both of you 😉
Jesper
Is there a pic of what you are asking about? Maybe one at: https://www.google.com/search?q=via...wBFsQ_AUoAXoECAEQAw&biw=1506&bih=616&dpr=1.25
Good morning, Mark ... & thanks for following up on this with the link. As it is what I am looking for is shown in the first picture of the google search you linked to (just in case google doesn't search identically in different parts of the world it is also shown in the first link in my post #1). I just can't find any mention of how it changes the trace impedance although I reckon it must do so ... ???
Anyway, just in case somebody is interested, I also found this article the other day which describes the advantages of a close & tight trace via stitching in terms of trace bandwidth & linearity (from p. 12):
https://mpd.southwestmicrowave.com/...t-Boards-for-50-GHz-End-Launch-Connectors.pdf
And then a bit of feedback that I forgot in relation to your previous post:
Hmmm ... I think there are many aspects to this but if one believes in the advantages of low jitter / phase noise (as I do) it seems to me that the devices with the lowest phase noise (74AC, 74AUP, NC7, et al.) are all very high speed devices with low rise / fall times. Thus, I don't really see any way around it than to try to layout the boards to cope with these speedy ICs ... IMHO not easy - but on the other hand an interesting challenge. However, also realizing that at these low phase noise values even slight trace reflections may be important I would like to find some information about how this via stitching influences the trace impedance.
Well, anyway - cheers from Denmark,
Jesper
Anyway, just in case somebody is interested, I also found this article the other day which describes the advantages of a close & tight trace via stitching in terms of trace bandwidth & linearity (from p. 12):
https://mpd.southwestmicrowave.com/...t-Boards-for-50-GHz-End-Launch-Connectors.pdf
And then a bit of feedback that I forgot in relation to your previous post:
Hmmm ... I think there are many aspects to this but if one believes in the advantages of low jitter / phase noise (as I do) it seems to me that the devices with the lowest phase noise (74AC, 74AUP, NC7, et al.) are all very high speed devices with low rise / fall times. Thus, I don't really see any way around it than to try to layout the boards to cope with these speedy ICs ... IMHO not easy - but on the other hand an interesting challenge. However, also realizing that at these low phase noise values even slight trace reflections may be important I would like to find some information about how this via stitching influences the trace impedance.
Well, anyway - cheers from Denmark,
Jesper
Hi Jesper,
Regarding jitter and rise time, that stuff really only matters in one place, the I2S and clock signals arriving at the dac (well maybe at an ASRC too, but let's not go there for now). If you reclock just before the dac, the clock signal driving the reclocker and the signals going to the dac are the ones we are mainly interested in.
The next thing to consider is that engineering is often an art (as in 'The Art of Electronics'). There are tradeoffs that may need to be optimized. Jitter is only one factor. So is substrate coupled noise in a mixed signal chip like a dac (and its not 74AC so far as I know). In addition dac chips are sometimes sensitive to timing of signals in a subtle way that the manufacturer doesn't tell you about (as Syn08 found out about with an ADC he was designing).
The point is that for those most critical digital signals, don't be afraid to experiment and listen. Exact optimal damping resistor values will vary with layout, and there is not simple formula to figure out in advance exactly what will sound best. For jitter it may be best to test with DSD since it is more sensitive to jitter than PCM.
The history on this from my perspective is that I first learned about overdamping dac clock and or I2S lines from John Westlake. It was much later I found out that Wadia used the same experimental methods I described above on their famous dacs that used the same chips everyone else could get.
So what I would suggest is don't be lazy. Build a dac with standard 33R series damping resistors, then try 100R on, say, MCLK. Any difference? If you don't hear any difference then maybe your dac and or your system have other, bigger problems. Or maybe it doesn't matter for you dac. The thing is, if you don't try you will never know if you made the best tradeoff decision or not.
Mark
Regarding jitter and rise time, that stuff really only matters in one place, the I2S and clock signals arriving at the dac (well maybe at an ASRC too, but let's not go there for now). If you reclock just before the dac, the clock signal driving the reclocker and the signals going to the dac are the ones we are mainly interested in.
The next thing to consider is that engineering is often an art (as in 'The Art of Electronics'). There are tradeoffs that may need to be optimized. Jitter is only one factor. So is substrate coupled noise in a mixed signal chip like a dac (and its not 74AC so far as I know). In addition dac chips are sometimes sensitive to timing of signals in a subtle way that the manufacturer doesn't tell you about (as Syn08 found out about with an ADC he was designing).
The point is that for those most critical digital signals, don't be afraid to experiment and listen. Exact optimal damping resistor values will vary with layout, and there is not simple formula to figure out in advance exactly what will sound best. For jitter it may be best to test with DSD since it is more sensitive to jitter than PCM.
The history on this from my perspective is that I first learned about overdamping dac clock and or I2S lines from John Westlake. It was much later I found out that Wadia used the same experimental methods I described above on their famous dacs that used the same chips everyone else could get.
So what I would suggest is don't be lazy. Build a dac with standard 33R series damping resistors, then try 100R on, say, MCLK. Any difference? If you don't hear any difference then maybe your dac and or your system have other, bigger problems. Or maybe it doesn't matter for you dac. The thing is, if you don't try you will never know if you made the best tradeoff decision or not.
Mark
Last edited:
Hi Mark ... Good feedback, many thanks 😉
Hmmm ... I think it would be fair to say that I am not lazy (I know you didn't think I was lazy per se 😉 ) I just need a good starting point for my decisions on a DAC or ADC design .... Eric Bogatin in one of Robert Feranec's videos illustrates how mismatched parts of a signal line (transmission part, traces, connectors, receiving end) all cause reflections that bounce back & forth. Nothing new about this - I just hadn't before realized that it continues for quite a while - something that I reckon could influence the performance of the DAC/ADC (and maybe such mismatches may even have quite a say in determining a DAC's sound?).
Overdamping the transmitted signal doesn't really change this - even if using e.g. a 100 ohm series resistor instead of, say, 37 ohms will attenuate the reflections faster than 37 ohms. But I agree entirely with you that the ultimate arbiter will be listening and I intend to replace resistors and hear if / what difference there may be. Looking forward to it, actually.
I reckon though that another aspect of overdamping the data lines to the DAC could be what you call "substrate coupled noise". Damping the data lines (likely?) will have the effect that the IC intrinsically coupled digital noise attenuates ... Hmmm ... Although I have not studied the AK4499exeq datasheet in detail I reckon that if it were possible to "slowly" load the data signals to the DAC and then just have the important digital signal (MCLK or BCLK or LRCK?) arrive at high speed it could indeed be an advantage ...
Things to ponder (I will send you a short PM later in the day).
Thanks again for your feedback, Mark.
Jesper
Hmmm ... I think it would be fair to say that I am not lazy (I know you didn't think I was lazy per se 😉 ) I just need a good starting point for my decisions on a DAC or ADC design .... Eric Bogatin in one of Robert Feranec's videos illustrates how mismatched parts of a signal line (transmission part, traces, connectors, receiving end) all cause reflections that bounce back & forth. Nothing new about this - I just hadn't before realized that it continues for quite a while - something that I reckon could influence the performance of the DAC/ADC (and maybe such mismatches may even have quite a say in determining a DAC's sound?).
Overdamping the transmitted signal doesn't really change this - even if using e.g. a 100 ohm series resistor instead of, say, 37 ohms will attenuate the reflections faster than 37 ohms. But I agree entirely with you that the ultimate arbiter will be listening and I intend to replace resistors and hear if / what difference there may be. Looking forward to it, actually.
I reckon though that another aspect of overdamping the data lines to the DAC could be what you call "substrate coupled noise". Damping the data lines (likely?) will have the effect that the IC intrinsically coupled digital noise attenuates ... Hmmm ... Although I have not studied the AK4499exeq datasheet in detail I reckon that if it were possible to "slowly" load the data signals to the DAC and then just have the important digital signal (MCLK or BCLK or LRCK?) arrive at high speed it could indeed be an advantage ...
Things to ponder (I will send you a short PM later in the day).
Thanks again for your feedback, Mark.
Jesper
One more point, what I am calling overdamping doesn't necessarily damp reflections faster. That's because the 100R resistor causes reflections too. The more it looks like a lump of Z on the line that does not match the line Z, the more energy will be reflected. To better understand I would suggest looking up Time Domain Reflectometry (TDR). App notes may show diagrams of what happens.
Also of course, a long line (relative to rise time and the speed of light in the PCB trace) would be expected to show more reflection problems than a short line. The lines we might want to damp between the last reclocker and the dac chip are usually fairly short in that respect. In that case we wouldn't expect to see much in the way of significant mismatch reflections.
Besides, I looked at the clock signal arriving at the dac with a fairly high speed scope and active low-capacitance probe. I didn't see any reflection problems up at several hundred MHz. The net effect is that rise-time is slowed a little, and the clock edge is delayed a little. Also, I will add something to what I said previously: all line damping doesn't have to be in one place. Say, for example, half of it could be in the middle of the line. When causing a line to have have non-uniform impedance that way it can help to distribute damping, perhaps all the more so if the line is starting to look a bit long.
Also of course, a long line (relative to rise time and the speed of light in the PCB trace) would be expected to show more reflection problems than a short line. The lines we might want to damp between the last reclocker and the dac chip are usually fairly short in that respect. In that case we wouldn't expect to see much in the way of significant mismatch reflections.
Besides, I looked at the clock signal arriving at the dac with a fairly high speed scope and active low-capacitance probe. I didn't see any reflection problems up at several hundred MHz. The net effect is that rise-time is slowed a little, and the clock edge is delayed a little. Also, I will add something to what I said previously: all line damping doesn't have to be in one place. Say, for example, half of it could be in the middle of the line. When causing a line to have have non-uniform impedance that way it can help to distribute damping, perhaps all the more so if the line is starting to look a bit long.
Instead of guessworking by listening there are techical resources to help with line termination. BTW it is better to use proper terminology (i.e. series termination resistor, not damping resistor) as it helps in finding resources.
E.g.
https://www.ti.com/lit/an/scaa045a/scaa045a.pdf
https://www.intel.com/content/www/u...uideline-use-series-termination-resistor.html
http://www.interfacebus.com/Design_Termination.html
E.g.
https://www.ti.com/lit/an/scaa045a/scaa045a.pdf
https://www.intel.com/content/www/u...uideline-use-series-termination-resistor.html
http://www.interfacebus.com/Design_Termination.html
Here's one guy's thoughts on the matter:
https://www.diyaudio.com/community/threads/low-noise-regulator-for-dac-clock.304013/post-6690283
https://www.diyaudio.com/community/threads/low-noise-regulator-for-dac-clock.304013/post-6690289
https://www.diyaudio.com/community/threads/low-noise-regulator-for-dac-clock.304013/post-6690297
Basically, its the first post and next few posts that follow.
Some additional practical experince:
https://www.diyaudio.com/community/...trumentation-applications.347854/post-6524953 Although it that case the manufacturer did provide info on timing requirements.
They don't always tell you everything though, like about hump distortion.
https://www.diyaudio.com/community/threads/low-noise-regulator-for-dac-clock.304013/post-6690283
https://www.diyaudio.com/community/threads/low-noise-regulator-for-dac-clock.304013/post-6690289
https://www.diyaudio.com/community/threads/low-noise-regulator-for-dac-clock.304013/post-6690297
Basically, its the first post and next few posts that follow.
Some additional practical experince:
https://www.diyaudio.com/community/...trumentation-applications.347854/post-6524953 Although it that case the manufacturer did provide info on timing requirements.
They don't always tell you everything though, like about hump distortion.
Last edited:
The example in Post #1 looks like a pair of differential traces running on a layer that also has a ground plane. The vias are intended to keep all of the ground plane grounded (assuming there're multiple ground planes in the PCB) even at RF. Without them you could have a standing wave in the ground plane which would not be very ground-like. Even with the vias you can still have standing waves, they'd just be of much, much higher frequency. 🙂
The vias should change the impedance of the traces a little bit due to the capacitance between the via 'tube' as it goes through the board and the trace itself. Basically the vias would add a little bit of fringe capacitance. I doubt it's much, though, as the distance from the traces to the vias (think 3D through the prepreg) is pretty long relative to the space from the traces to the ground plane (or between traces).
Stippled ground planes are common in the RF world and some take this to mean this technique should be applied in analog audio circuits as well. Some go as far as to pepper the planes/pours with vias. I have a sneaky suspicion that they end up shooting themselves in the foot that way as it increases the ground impedance rather than lowering it.
Anyway. That's my hand-wavey explanation. Hope it makes sense.
Tom
The vias should change the impedance of the traces a little bit due to the capacitance between the via 'tube' as it goes through the board and the trace itself. Basically the vias would add a little bit of fringe capacitance. I doubt it's much, though, as the distance from the traces to the vias (think 3D through the prepreg) is pretty long relative to the space from the traces to the ground plane (or between traces).
Stippled ground planes are common in the RF world and some take this to mean this technique should be applied in analog audio circuits as well. Some go as far as to pepper the planes/pours with vias. I have a sneaky suspicion that they end up shooting themselves in the foot that way as it increases the ground impedance rather than lowering it.
Anyway. That's my hand-wavey explanation. Hope it makes sense.
Tom