Thank you. The negative feedback needs some higher resistor values at the gate, I guess. I'm afraid, that this will add some extra noise you can avoid with some of the other circuits.
I recommend you do a few signal-to-noise ratio calculations. For example
The voltage noise density of a 10K resistor at room temperature is 12.9 nanovolts per root Hz. With a measurement bandwidth of 44 kHz that's 2.70 microvolts RMS of noise. With an input (and output) of 1V RMS, the resulting signal-to-noise ratio is 20 * log10(1V / 2*2.7uV) = 105 dB.
Recall that a 1*LSB error in a 16 bit DAC gives a signal-to-noise ratio of 96.3 dB. So this 10K resistor, operating at signal levels one quarter of the maximum swing, at room temperature, gives a better signal-to-noise ratio than the quantization error of a 16 bit DAC.
- Bandwidth of SNR measurement: 44 kHz
- Output level: 1V RMS
- Series resistance: 10 Kohms
- Temperature: 300K
Recall that a 1*LSB error in a 16 bit DAC gives a signal-to-noise ratio of 96.3 dB. So this 10K resistor, operating at signal levels one quarter of the maximum swing, at room temperature, gives a better signal-to-noise ratio than the quantization error of a 16 bit DAC.
Not referring to any, but 11 and 16 seems like in thd-2 cancelation arrangement. Series and parallel version kind off.
I agree with reply #4 , doesn't make sense to use JFET if minimum distortion is in priority list. To get right THD numbers you have to build discrete OPA using twice more components compare to BJT, this explains absence of pure JFET OPA.
JFET is good for exactly opposite - to Generate distortion. Same way and fashion as tubes do.
If your OK with the distortion profile, something like this is the first thing that come to mind:
Output level is 6Vp-p at 0.12% THD.
Output level is 6Vp-p at 0.12% THD.
Thanks, I have to compare all your proposals im more details later, but thanks for the great input.
It's right that JFETs are not the right choice to get very low THD. But actually my current design is an all JFET amplifier without global feedback and I was looking for the solution providing lowest possible THD using JFETs. But it’s early in the design phase, and maybe there will come the time I will think about my initial goal and change it.
A good Opamp will be better in most of the measurements and simulations, but that's too easy, isn't it. 😉
It's right that JFETs are not the right choice to get very low THD. But actually my current design is an all JFET amplifier without global feedback and I was looking for the solution providing lowest possible THD using JFETs. But it’s early in the design phase, and maybe there will come the time I will think about my initial goal and change it.
A good Opamp will be better in most of the measurements and simulations, but that's too easy, isn't it. 😉
Well, you may want to inform us about some more design requirement of this inverter stage other than the 4Vpp max signal level, notably the required minimum input impedance and required maximum output impedance and drive capabilities, and maybe noise limits as well.
About 0.02% 4Vpp. But you realize a decent op-amp will do this with much less THD and better buffering, fewer parts.
And an NPN bipolar circuit will outperform it substantially too... Not sure I understand the motivation in this one other than the sport of getting best performance under constraints, which would still be "implement an opamp using only n-FETs" - we'd be looking for gain of 100dB or more for that, and I am sure the challenge then becomes one of stabilizing a multi-stage design.
Hey @jenimitso, you are absolutely right. I have built lots of systems in exactly this common way and they all sound great, at least for me. The only reason for me is… I like to have some fun with the design. I like discrete analog designs and try to find their optimum and not going well-known, proven, best performing, common, cheapest or easiest ways. I like to build things that are new for me. And if it ends with a design I like… I made everything right and don’t need to comparing measurement results. Music is emotion…. and analog design for me as well, somehow.
Anyway, I’m familiar with OPAs, use them a lot in my job but sometimes I like to play with other, maybe older techniques and circuits. That’s all.
Actually I’m designing a phono amplifier and try to stay without feedback. Not because I think it will provide better measurement results. I know that this isn’t true. All my others phono amps use feedback, use discrete JFET inputs but OPAs for filtering, servos… and so on. But not this time, or let’s say, not at the moment. I’m still working at the schematic and doing lot’s of simulations.
And to be honest again, I’m pretty sure I will not hear a difference if both channels are inverted or not, as long as they are equal. Maybe I will solder a jumper above the inverting stage but before, I like to see how it works. 😊
Thank you to all of you for your great support. At the moments @KSTR 's proposal with some addaptions provide good results for me.
Sorry, I didn't notice that somebody ask. 😛
It's said above, sorry that I don't provide enough information. It's for a phono stage where I like to have a "direct and discrete JFET path". There will be a switch to an OP inverter as well that provides additional amplification, but also the so called JFET path.
So that you understand a little better who I am... my phono cables cost about 20€. 🤣 I'm not an audio esoteric and I don't believe that magic or voodoo stuff sounds better because it's more expensive. And yes, I use standard PP film capacitors because they sound great and not some hocus-pocus for a lot of money. [Sarcasm, no offense intended!]
I like music and electronic design, that's why I'm here.
Sorry @KSTR, I really didn't notice your question. 🥵
I use an JFET inverting high gain amplifier at the input of the phono stage. The only reason I'm working at this inverter stage is to bring the signal back to the "correct" phase, knowing that it should not be necessary at all. The input voltage will be smaller but I try to stay at acceptable THD below 4Vpp.
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...and the inverter is after this stage, with a higher input impedance buffer between. But I'm currently trying to go without this buffer.
What do you mean, maybe you got me wrong or my explanation wasn't that good, sorry.
All you said before was right and the mu-follower as input stage is working great. But it's inverting the signal and that's the reason I'm thinking about this inverter.
All you said before was right and the mu-follower as input stage is working great. But it's inverting the signal and that's the reason I'm thinking about this inverter.
So what is the design objectives ?
Gain -1, Single Supply 30V, NJFETs, Zero Global Feedback (ZGF) ? Preferably low distortion for 4Vpp ?
For a simple circuit with ZGF, a phase splitter followed by Source follower comes to mind.
But the supply voltage sets some limitations to the phase splitter.
The JFET sees the fully 4V swing at maximum input.
So it needs at least 7~8V across D-S at no signal.
The drain resistor has to be a touch higher than the source resistor to be truly inverted unity gain.
So they should get ~6.5V and ~6V respectively.
The bias is determined by the resistor values. Let's say 4mA as a starting value.
The source resistor is then 1.5k, and 1/Yfs of the JFET is roughly 40R.
That basically determines the amount of distortion at the output.
For 20V, H2 is about 0.05%, and H3 ~10x lower. Tube sound.
At 30V, the values can be halved.
It is known that some BJTs can have low Vce_sat and little Early effect.
And the gm is higher than JFET at the same bias.
As can be seen, the BJT circuit with 20V supply can have half the H2.
Which one would I choose ?
If I can have 30V, I would use NJFET, as H3 is 10dB lower than the BJT version.
If I am stuck with 20V, then no choice but to use BJT for the splitter.
BTW, you don't need to buy expensive 2SK170, and for sure not LSK170.
Just wire a 2SK2145GR in parallel and use as K170GR replacement.
www.diyaudio.com/community/threads/njfets-for-source-follower-applications.329131/
Cheers,
Patrick
.
Gain -1, Single Supply 30V, NJFETs, Zero Global Feedback (ZGF) ? Preferably low distortion for 4Vpp ?
For a simple circuit with ZGF, a phase splitter followed by Source follower comes to mind.
But the supply voltage sets some limitations to the phase splitter.
The JFET sees the fully 4V swing at maximum input.
So it needs at least 7~8V across D-S at no signal.
The drain resistor has to be a touch higher than the source resistor to be truly inverted unity gain.
So they should get ~6.5V and ~6V respectively.
The bias is determined by the resistor values. Let's say 4mA as a starting value.
The source resistor is then 1.5k, and 1/Yfs of the JFET is roughly 40R.
That basically determines the amount of distortion at the output.
For 20V, H2 is about 0.05%, and H3 ~10x lower. Tube sound.
At 30V, the values can be halved.
It is known that some BJTs can have low Vce_sat and little Early effect.
And the gm is higher than JFET at the same bias.
As can be seen, the BJT circuit with 20V supply can have half the H2.
Which one would I choose ?
If I can have 30V, I would use NJFET, as H3 is 10dB lower than the BJT version.
If I am stuck with 20V, then no choice but to use BJT for the splitter.
BTW, you don't need to buy expensive 2SK170, and for sure not LSK170.
Just wire a 2SK2145GR in parallel and use as K170GR replacement.
www.diyaudio.com/community/threads/njfets-for-source-follower-applications.329131/
Cheers,
Patrick
.
...but lot’s of gain. At the moment there's only one mu-follower and one inverter. Do you think two mu-follower with reduced gain are a better option?