Why?
At the bias current levels specified a single JFE150 ($2.47) is more expensive and significantly noisier than a combination of 5 2SK209GRs ($2.10), even with a worst-case miss-match between the devices. Two or three JFE150s per channel could be justified on the basis of noise, but the benefit is minimal, and the cost is much higher.
The OPA192 is $3+ vs $0.64 for the OPA202 and there are no aspects of the OPA192 that are more desirable in this design. Indeed, the one thing that does really matter- the 1/f noise- is much worse in the OPA192 than the OPA202.
The "thumbs up"s suggest that there are those who think differently.
Please explain your justifications, as I'm always willing to learn.
At the bias current levels specified a single JFE150 ($2.47) is more expensive and significantly noisier than a combination of 5 2SK209GRs ($2.10), even with a worst-case miss-match between the devices. Two or three JFE150s per channel could be justified on the basis of noise, but the benefit is minimal, and the cost is much higher.
The OPA192 is $3+ vs $0.64 for the OPA202 and there are no aspects of the OPA192 that are more desirable in this design. Indeed, the one thing that does really matter- the 1/f noise- is much worse in the OPA192 than the OPA202.
The "thumbs up"s suggest that there are those who think differently.
Please explain your justifications, as I'm always willing to learn.
Because
1) FET noise is inversely proportional to the square root of the transconductance (Yfs or Gfs) = 15 ms @ 2SK209 (75 ms if 5 || without missmatch) and 68 ms @ JFE150 . The price of 100 2SK209 needed for 5 matched is much more than $2.
2) you use OPA202 as DC servo: +-25 uV offset vs +-5 uV offset @ OPA192 . (your 220 nF feedback makes noise negligible both of OPA202 & OPA192)
1. No matching is required. Because of the square law characteristic, the net gm and hence noise resulting from putting five 2sK209GRs in parallel where the source current is effectively a constant value barely changes as the devices randomly range from the min to max within the manufacturer's selection range. I tested this in simulation by building models that reflect the boundaries of the selection specs that the manufacturer makes, in addition to the published "nominal" model, and "measuring" gm, noise etc. as the devices are shifted through the range from min to nominal to max IDSS|vgs=0. This included having combinations such as, all min IDSS, all max IDSS, one min plus 4 max, 2 min plus 3 max, etc. etc. using the min, max and nominal models, and "measuring" the device current sharing, overall gm and noise for the design. In reality the GR selection, if I remember correctly, amounts to a variation of about 250mv in Vt for the devices.
A moment's thought would indicate that a constant current sourcing ID for the "composite" input FET would result (ignoring "second order" effects) in identical results for gm and noise at the extremes where all of one bound or other in the FET selection has been made.
This is a benefit of the chosen architecture, as opposed to say, the one employed in the Pearl 3 design.
Also, no degeneration Rs are required. The effect on stabilizing the current per device is small and the degradation in noise is significant.
Finally, the theoretical result has proven to be practically correct in the measured results of several units manufactured by myself and others from "randomly" selected FETs from the Toshiba GR band.
2. The offset introduced by the DC servo only causes a shift in the voltage at the inverting port-i.e. across the feedback R to ground. It has no effect on the output DC value which is set by the offset of the OPA1656 at +/- 0.5mv, I believe.
c. 200uv at the inverting input translates out to c.40ua for the 5ohm to ground R, which is negligible compared to the input stage bias current of c. 11ma that it contributes to, causing irrelevant changes in gm and noise for the input stage.
Indeed, the action of the servo is intended purely to force the current in the input stage be behave like a constant current source, without using giant caps.
The servo loop 1/f noise can contribute directly to the LF noise of the amp, dependent on the spectral content and the input RC time constant. This may not affect the A weighted value very much but can contribute to the broadband LF noise which can be amplified by wide bandwidth audio systems (such as my own) which have significant sub sonic response. This can result in unwanted woofer excursions.
In general, these questions could be answered by simulation. Did you try simulating the design and incorporating suitable models for the FETs?
A moment's thought would indicate that a constant current sourcing ID for the "composite" input FET would result (ignoring "second order" effects) in identical results for gm and noise at the extremes where all of one bound or other in the FET selection has been made.
This is a benefit of the chosen architecture, as opposed to say, the one employed in the Pearl 3 design.
Also, no degeneration Rs are required. The effect on stabilizing the current per device is small and the degradation in noise is significant.
Finally, the theoretical result has proven to be practically correct in the measured results of several units manufactured by myself and others from "randomly" selected FETs from the Toshiba GR band.
2. The offset introduced by the DC servo only causes a shift in the voltage at the inverting port-i.e. across the feedback R to ground. It has no effect on the output DC value which is set by the offset of the OPA1656 at +/- 0.5mv, I believe.
c. 200uv at the inverting input translates out to c.40ua for the 5ohm to ground R, which is negligible compared to the input stage bias current of c. 11ma that it contributes to, causing irrelevant changes in gm and noise for the input stage.
Indeed, the action of the servo is intended purely to force the current in the input stage be behave like a constant current source, without using giant caps.
The servo loop 1/f noise can contribute directly to the LF noise of the amp, dependent on the spectral content and the input RC time constant. This may not affect the A weighted value very much but can contribute to the broadband LF noise which can be amplified by wide bandwidth audio systems (such as my own) which have significant sub sonic response. This can result in unwanted woofer excursions.
In general, these questions could be answered by simulation. Did you try simulating the design and incorporating suitable models for the FETs?
Other things.
The design started with multiple JFE150s. The gm for the JFE150 at IDSS =11ma is according to the datasheet (fig 6.4) about 30mS, whereas the gm for the 2sK209 was about 14mS at 2.2ma (datasheet fig) providing 70mS for 5 at 11 mA.
The gm for the JFE150 is fairly similar to that of the 2SK209- at a given current. The datasheet gm of the JFE150 at 2ma is 18ms, or, scaled, about 19mS at 2.2ma.
I dealt with the matching issue of the multiple JFE150s by using dual JFE150s- the JFE2140 - and enclosing each in a separate DC loop as the Vt variation is quite large at 0.6v rather than the 0.25v of the GR selection and is not amenable to the simpler approach.
The 2SC209GR choice thus enabled a much cheaper, simpler, approach.
The design started with multiple JFE150s. The gm for the JFE150 at IDSS =11ma is according to the datasheet (fig 6.4) about 30mS, whereas the gm for the 2sK209 was about 14mS at 2.2ma (datasheet fig) providing 70mS for 5 at 11 mA.
The gm for the JFE150 is fairly similar to that of the 2SK209- at a given current. The datasheet gm of the JFE150 at 2ma is 18ms, or, scaled, about 19mS at 2.2ma.
I dealt with the matching issue of the multiple JFE150s by using dual JFE150s- the JFE2140 - and enclosing each in a separate DC loop as the Vt variation is quite large at 0.6v rather than the 0.25v of the GR selection and is not amenable to the simpler approach.
The 2SC209GR choice thus enabled a much cheaper, simpler, approach.
Last edited:
To illustrate, below are the simulated results using two "corner" models for the 209/2145.
One is for an IDSS/vgs=0 case of 2.6mA (GRL), and one for the case of 6.5mA (GRH). These represent the extremes of the "green" device selection by Toshiba. Although it's not catastrophic to operate these FETs with positive VGS it's less than ideal (although Pass has been known to deliberately do it), the choice of 5, or more, FETs avoids this problem as long as IDSS is less than 13mA.
The difference in Vt for these devices is c. 265mv (-0.385v to -0.65v). These values are consistent with the datasheet curves if you extrapolate them a tad.
I can plug the models into the simulations to see variations in noise etc.
Let's see what happens to the noise as the low Vt devices are replaced with the high Vt devices.
I'll use the 2 ohm case with the transimpedance design mentioned previously (post #314) as I have the simulation set up and specify the 1kHz NSD at the output of the gain stage.
The closed loop gain is 710.8. This is essentially independent of the FET choice.
1. 0 GRH, 5 GRL NSD=599.4pv/rtHz ID 2.25ma/device.
2. 1GRH, 4 GRL NSD= 607.5pv/rtHz ID 4.97ma, 1.60ma
3. 2GRH, 3 GRL NSD= 612.9pv/rtHz ID 4.1ma, 1.06ma
4. 3GRH, 2 GRL NSD= 613.6pv/rtHz ID 3.37ma, 0.67ma
5. 4GRH, 1 GRL NSD= 608.6pv/rtHz ID 2.77ma, 0.38ma
6. 5GRH, 0 GRL NSD= 597.6pv/rtHz ID 2.30ma/device
So, 0.2dB variation in noise over ALL possible combinations of the two choices.
One is for an IDSS/vgs=0 case of 2.6mA (GRL), and one for the case of 6.5mA (GRH). These represent the extremes of the "green" device selection by Toshiba. Although it's not catastrophic to operate these FETs with positive VGS it's less than ideal (although Pass has been known to deliberately do it), the choice of 5, or more, FETs avoids this problem as long as IDSS is less than 13mA.
The difference in Vt for these devices is c. 265mv (-0.385v to -0.65v). These values are consistent with the datasheet curves if you extrapolate them a tad.
I can plug the models into the simulations to see variations in noise etc.
Let's see what happens to the noise as the low Vt devices are replaced with the high Vt devices.
I'll use the 2 ohm case with the transimpedance design mentioned previously (post #314) as I have the simulation set up and specify the 1kHz NSD at the output of the gain stage.
The closed loop gain is 710.8. This is essentially independent of the FET choice.
1. 0 GRH, 5 GRL NSD=599.4pv/rtHz ID 2.25ma/device.
2. 1GRH, 4 GRL NSD= 607.5pv/rtHz ID 4.97ma, 1.60ma
3. 2GRH, 3 GRL NSD= 612.9pv/rtHz ID 4.1ma, 1.06ma
4. 3GRH, 2 GRL NSD= 613.6pv/rtHz ID 3.37ma, 0.67ma
5. 4GRH, 1 GRL NSD= 608.6pv/rtHz ID 2.77ma, 0.38ma
6. 5GRH, 0 GRL NSD= 597.6pv/rtHz ID 2.30ma/device
So, 0.2dB variation in noise over ALL possible combinations of the two choices.
Really ?
Really ?
OPA192 en= 5.5 nV/sqrtHz OPA202 en=9 nV/sqrtHz. OPA192 has jfet input with 1.5 fA/sqrtHz noise current, OPA202 input bipolars have 0.076 pA/rootHz noise cirrent, it means OPA202 on your R48=150k makes (Ohm`s law) noise voltage 0.076x150=11.4 nV/sqrtHz, i.e. = 14.5 nV/sqrtHz with en=9 nV/sqrtHz. It is 3 times bigger than OPA192.I wish you good luck with paralleling unmatched 2SK209
The broadband NSD of the servo opamp is essentially irrelevant as the servo loop bandwidth is so low (the low bandwidth cutoff is in the 100 milli Hz range), so the effective "noise gain" in the frequency region where the broadband NSD matters is extremely low and does not contribute significantly to the equivalent preamp input NSD.
The 1/F noise IS important. How about running some sims or at least trying to get some detailed understanding of how the circuit actually works? I have not run any with your opamp of choice, but I have run them with OPA1656s etc. with noticeably inferior results to the OPA202, and for exactly the described reasons.
Similarly, as far as the unmatched FETs are concerned. I showed the simulation results, I explained the theory, I did the measurements.
It works. No praying required. How about showing what is wrong with any of the above? Just because it is contrary to your perspective does not make it wrong...
The 1/F noise IS important. How about running some sims or at least trying to get some detailed understanding of how the circuit actually works? I have not run any with your opamp of choice, but I have run them with OPA1656s etc. with noticeably inferior results to the OPA202, and for exactly the described reasons.
Similarly, as far as the unmatched FETs are concerned. I showed the simulation results, I explained the theory, I did the measurements.
It works. No praying required. How about showing what is wrong with any of the above? Just because it is contrary to your perspective does not make it wrong...
I wrote exactly the same thing in message #322 . Moreover, in your circuit the DС servo cascade is absolutely useless, since you have a separating capacitor at the JFETS input
Let's try it this way.
Remove the input servo. What happens?
The "FET" gate voltage goes to ground (more or less), and the "FET" source goes to whatever it needs to go to in order to support the current flowing into it.
However, the current is NOT from a current source. It is produced by three resistors- a small resistor to ground (5 ohms) in parallel with a 1.2k resistor to about -13v and the 1k current feedback resistor to the output of the OPA1656.
The OPA1656 is AC coupled so it is unity gain at DC and the output DC voltage is set by the opamp offset at +/-0.5mv max.
So far so good. Now what does this imply? if the 5ohm R was not present the variations in the "FET" would have minimal effect- the current would be almost constant as the Vt variations are much smaller than the voltage across the 1.2k R, and the feedback resistor comes from a essentially zero voltage.
However, if the 5ohm R is inserted this situation changes. The 5 ohm means that the bias current no longer approximates a current source- the Vt variations appear, to a first order, directly across the resistor causing significant variations in the bias current. This has unfortunate effects. It can crash the bias chain.
So, there seemingly are two options to make this work- you can put a giant cap to ground in series with the 5ohm R (yuk!) or you can, as happens in this case, adjust the FET DC gate potential to put zero volts, or there about, across the 5 ohm resistor. The voltage across the 5 ohm is not so critical, but it should be low in order to not cause the bias current to vary too much. 0.5 mv changes the bias by about 100ua or about 1% of the total, so that seems like a decent max. Below that, it really does not matter. That being the case the OPA202 with an offset of c. 300uv, including the 150k IR drop, seems like a solid choice.
The servo itself is interesting, because of the "integrating" cap and the input coupling cap- it is a second order system, and the loop gain and stability varies as the equivalent resistance to ground from the inverting input node (the FET source) changes, so when the value of that resistance changes from the MC mode to the MM mode the loop dynamics change- and care was taken to ensure stable operation.
Now let's look at the integrated noise of the buffer with an OPA1656 vs an OPA202.
First the OPA1656, then the OPA202.
As can be seen, the difference is in the ULF content- exactly that which causes undesirable woofer displacements if not curtailed.
Not a big deal, but certainly there is no reason to insert a more expensive opamp that makes it worse and provides, in my opinion, no tangible benefit.
Remove the input servo. What happens?
The "FET" gate voltage goes to ground (more or less), and the "FET" source goes to whatever it needs to go to in order to support the current flowing into it.
However, the current is NOT from a current source. It is produced by three resistors- a small resistor to ground (5 ohms) in parallel with a 1.2k resistor to about -13v and the 1k current feedback resistor to the output of the OPA1656.
The OPA1656 is AC coupled so it is unity gain at DC and the output DC voltage is set by the opamp offset at +/-0.5mv max.
So far so good. Now what does this imply? if the 5ohm R was not present the variations in the "FET" would have minimal effect- the current would be almost constant as the Vt variations are much smaller than the voltage across the 1.2k R, and the feedback resistor comes from a essentially zero voltage.
However, if the 5ohm R is inserted this situation changes. The 5 ohm means that the bias current no longer approximates a current source- the Vt variations appear, to a first order, directly across the resistor causing significant variations in the bias current. This has unfortunate effects. It can crash the bias chain.
So, there seemingly are two options to make this work- you can put a giant cap to ground in series with the 5ohm R (yuk!) or you can, as happens in this case, adjust the FET DC gate potential to put zero volts, or there about, across the 5 ohm resistor. The voltage across the 5 ohm is not so critical, but it should be low in order to not cause the bias current to vary too much. 0.5 mv changes the bias by about 100ua or about 1% of the total, so that seems like a decent max. Below that, it really does not matter. That being the case the OPA202 with an offset of c. 300uv, including the 150k IR drop, seems like a solid choice.
The servo itself is interesting, because of the "integrating" cap and the input coupling cap- it is a second order system, and the loop gain and stability varies as the equivalent resistance to ground from the inverting input node (the FET source) changes, so when the value of that resistance changes from the MC mode to the MM mode the loop dynamics change- and care was taken to ensure stable operation.
Now let's look at the integrated noise of the buffer with an OPA1656 vs an OPA202.
First the OPA1656, then the OPA202.
As can be seen, the difference is in the ULF content- exactly that which causes undesirable woofer displacements if not curtailed.
Not a big deal, but certainly there is no reason to insert a more expensive opamp that makes it worse and provides, in my opinion, no tangible benefit.
Last edited:
ALERT!
For any builders out there, C50 (10uF, electrolytic) has the polarity mislabeled on the layout. It should be reversed, and if already installed it should be removed.
Replacement is not essential if removed, but if installed removal is essential.
For any builders out there, C50 (10uF, electrolytic) has the polarity mislabeled on the layout. It should be reversed, and if already installed it should be removed.
Replacement is not essential if removed, but if installed removal is essential.
Layout is generally the position of components and traces. Overlay is another term for the silk-screening.
Darn, my history as an IC designer pops up again.
This particular capacitor was wrongly identified on the board so that the plus and minus terminals were transposed.
i.e. the + notification/ white band on the board should actually be - and vice versa.
All that is required is that the part at issue is rotated 180 degrees about its vertical axis when inserted into the board.
When you consider that three separate sets of eyes were used to check this it's amazing that it wasn't caught earlier.
As a complete tangent, I've been asked to do a Neurochrome style multi paralleled LM3886 composite power amp. It's not something that I initially found especially interesting, but as is said- I take requests and a few interested parties were quite insistent.
I have a schematic and simulations. A critique would be appreciated as it's outside my usual purview, but I can just imagine the reaction- "Oh no, yet another composite LM3886 amp" which, to be honest, was my reaction at first.
I think that it's a bit different from normal- but then again what do I know.
If there is interest, I could post it here, then if worthwhile, move on to a separate thread as in this instance I don't even know what I don't know...
This particular capacitor was wrongly identified on the board so that the plus and minus terminals were transposed.
i.e. the + notification/ white band on the board should actually be - and vice versa.
All that is required is that the part at issue is rotated 180 degrees about its vertical axis when inserted into the board.
When you consider that three separate sets of eyes were used to check this it's amazing that it wasn't caught earlier.
As a complete tangent, I've been asked to do a Neurochrome style multi paralleled LM3886 composite power amp. It's not something that I initially found especially interesting, but as is said- I take requests and a few interested parties were quite insistent.
I have a schematic and simulations. A critique would be appreciated as it's outside my usual purview, but I can just imagine the reaction- "Oh no, yet another composite LM3886 amp" which, to be honest, was my reaction at first.
I think that it's a bit different from normal- but then again what do I know.
If there is interest, I could post it here, then if worthwhile, move on to a separate thread as in this instance I don't even know what I don't know...
The Gerbers and schematic files have been updated in the Dropbox.
https://www.dropbox.com/scl/fi/s1vf...ey=7jvoin2uq05l2zn54mi50t22z&st=uaqh0mhd&dl=0
https://www.dropbox.com/scl/fi/9qxa...ey=nsb2le30dz8dpyfl4a0thg8sq&st=u2afv1jp&dl=0
https://www.dropbox.com/scl/fi/s1vf...ey=7jvoin2uq05l2zn54mi50t22z&st=uaqh0mhd&dl=0
https://www.dropbox.com/scl/fi/9qxa...ey=nsb2le30dz8dpyfl4a0thg8sq&st=u2afv1jp&dl=0