the LMG1210 datasheet announce the unloaded rise time is 0.5ns.
however, my result is 10.7ns, if it needs to minus the deadtime, then it will be 10.7 - 8.4 = 2.3ns, that is pretty close.
the inductor may slow down the rise time, I am not sure the inductor is a load or not.
however, my result is 10.7ns, if it needs to minus the deadtime, then it will be 10.7 - 8.4 = 2.3ns, that is pretty close.
the inductor may slow down the rise time, I am not sure the inductor is a load or not.
The remaining 4 boards are functional after changing the PWM series resistor from 1k (accidentally set) to 3.3 ohms. The oscillation frequency is 2.4 MHz, with a static power consumption of about 12W. The dead time is set to 20 ns. The frequency will be 3.2MHz with after change the deadtime to 8ns.
An interesting finding is that the static power consumption does not change significantly, even with a wide range of oscillation frequency variations. strange!
An interesting finding is that the static power consumption does not change significantly, even with a wide range of oscillation frequency variations. strange!
Connected AMP to a speaker, and the sound is amazing!
Since there’s no heatsink yet, I only turned it on for about ten seconds at a time, then turned it off to allow the heat to dissipate before turning it on again.
The good news is that the aluminum housing and heatsink are on the way and should arrive in 2–3 days.
Since there’s no heatsink yet, I only turned it on for about ten seconds at a time, then turned it off to allow the heat to dissipate before turning it on again.
The good news is that the aluminum housing and heatsink are on the way and should arrive in 2–3 days.
The following two screenshots are from Icepower's website, demonstrating the hard switching losses of a GaN FET operating at 650 kHz, which amount to 3.18 W.
Using this data, we can calculate the loss per kilohertz as follows:
Loss/kHz = 3.18W/650 = 0.0049/kHz
If the switching frequency increases to 3.2 MHz, the total loss can be estimated as:
Total Loss=0.0049/kHz*3200kHz = 15.66W
A big high-five to myself! 🙂
Using this data, we can calculate the loss per kilohertz as follows:
Loss/kHz = 3.18W/650 = 0.0049/kHz
If the switching frequency increases to 3.2 MHz, the total loss can be estimated as:
Total Loss=0.0049/kHz*3200kHz = 15.66W
The switching loss of the AMP project appears to be reasonable, although the power rail voltage of the reference object is unknown.
A big high-five to myself! 🙂
I plan to write a thread titled "How High is Enough for Class D AMP Operating Frequency?", where I will analyze the impact of frequency on distortion and present numerical results to support my findings.
Welcome your ideas and perspectives—your input could provide valuable angles and insights to enrich my analysis and approach to this topic. Let’s collaborate!
Welcome your ideas and perspectives—your input could provide valuable angles and insights to enrich my analysis and approach to this topic. Let’s collaborate!
Have you considered the information beneath your feet as you walk.
Imagine over a decade of rigorous research and discussions on this forum, now archived (for the next success story), featuring contributions from Bruno Putzeys, Eva, and others. And here we are, returning to topics like the impact of frequency on distortion and the enduring 'No Feedback' debate and of recent the GaN vs Silicon tribes. Yet no updates on multi-loop dynamic feedback control, one poster a student moved the needle a few weeks ago I recall.
Imagine over a decade of rigorous research and discussions on this forum, now archived (for the next success story), featuring contributions from Bruno Putzeys, Eva, and others. And here we are, returning to topics like the impact of frequency on distortion and the enduring 'No Feedback' debate and of recent the GaN vs Silicon tribes. Yet no updates on multi-loop dynamic feedback control, one poster a student moved the needle a few weeks ago I recall.
I would greatly appreciate it if you could share any valuable insights or information regarding the relationship between operating frequency and distortion in Class D amplifiers.
At 2.1 MHz, the automotive market aimed to shrink amplifier sizes and integrate more channels. This switching target is deliberate, its side-channel interference at the 2.1 MHz sidebands is pushed into higher spectrum order due to environmental factors and to coexistence with other equipment/modules such as two-way radios, AM bands, EMI reduction in power delivery for ASICs, FPGAs, and other modern digital islands in a vehicle.
But wait can it be—are we here again a decade later... questioning whether higher speed equals better sound? No, the true focus lies in control theory and the intricacies of dynamic feedback loops. It's not just about achieving 100% modulation; it's about maintaining precision and stability while accounting for errors during the conversion process. These systems excel in compensating for non-linearities, ensuring that the output remains faithful to the intended signal even under challenging conditions. The essence of high-performance design here is not just speed but the ability to adapt, correct, and deliver consistent results, embodying the principles of advanced control engineering. This approach ensures that the fidelity of the audio signal remains uncompromised, proving that it's not speed alone, but the sophistication of control mechanisms, that drives better sound quality.
"But show me," you say. I respond, "You're on the right track for phase one. Your PCB design looks solid, but there’s still more work ahead.
Control, after all, is rooted in nature—everything has a dominant pole at 1/s"
But wait can it be—are we here again a decade later... questioning whether higher speed equals better sound? No, the true focus lies in control theory and the intricacies of dynamic feedback loops. It's not just about achieving 100% modulation; it's about maintaining precision and stability while accounting for errors during the conversion process. These systems excel in compensating for non-linearities, ensuring that the output remains faithful to the intended signal even under challenging conditions. The essence of high-performance design here is not just speed but the ability to adapt, correct, and deliver consistent results, embodying the principles of advanced control engineering. This approach ensures that the fidelity of the audio signal remains uncompromised, proving that it's not speed alone, but the sophistication of control mechanisms, that drives better sound quality.
"But show me," you say. I respond, "You're on the right track for phase one. Your PCB design looks solid, but there’s still more work ahead.
Control, after all, is rooted in nature—everything has a dominant pole at 1/s"
The housing arrived today. One module has been assembled, and everything fits well.
It can already drive a single speaker to enjoy music.
With my ear 'into' the speaker, I can’t hear any background noise.
The DC offset measures 2.8 mV.
It can already drive a single speaker to enjoy music.
With my ear 'into' the speaker, I can’t hear any background noise.
The DC offset measures 2.8 mV.
Assembled three more modules today. Unfortunately, I burned one due to misusing the thermal pad. 😳
Eventually, I managed to drive a pair of speakers. 🙂
The sound is crystal clear with incredible detail.
The static power consumption of the combination of the LMG1210 and EPC2001C is approximately 5.5W/MHz with a 48V power rail. Different deadtime settings may result in varying values.
Eventually, I managed to drive a pair of speakers. 🙂
The sound is crystal clear with incredible detail.
The static power consumption of the combination of the LMG1210 and EPC2001C is approximately 5.5W/MHz with a 48V power rail. Different deadtime settings may result in varying values.
It is to prevent AM interference and to squeak 0.005% thd out of it.
I am expecting about that thd from TPA3255 setup.
I am expecting about that thd from TPA3255 setup.
Congrats on the your DIY project! I am interested in your amplifier module, especially its impressive operating frequency of several MHz and the design without audio feedback. The design of PCB board looks very sexy 🙂
I’d like to DIY an amplifier myself. May I buy 2 modules? Would it also be possible for you to help me slightly increase the frequency? Thank you!
I’d like to DIY an amplifier myself. May I buy 2 modules? Would it also be possible for you to help me slightly increase the frequency? Thank you!
Seen like that ..... I would like the creator to coat it with a nice thick resin ... 🤣 🤣 🤣 🤣
Thank you so much for your interest in the amplifier module—I truly appreciate it. However, I must apologize, as a long-time follower of this thread has already ordered 2 modules, and I would like to keep the rest for myself at this time. I will definitely let you know if I decide to repopulate more modules in the future.
Regarding the operating frequency, I’m pretty sure it can run up to at least 4MHz, or even higher. The PCB is designed high-frequency material (lower dissipation factor), and the trace impedance is carefully controlled to allow for higher frequency operation. The only concern would be the static power due to high switching losses, but it should be manageable if you're comfortable using a larger heatsink.
Sorry to hear that, will wait for your next population. Happy holidays!
How High Should the Operating Frequency Be for a Class D Amplifier?
When considering the optimal operating frequency for a Class D amplifier, two contrasting ideas often emerge:
The diagram below illustrates the ideal sampling-and-hold process. In this scenario, the sampling time is effectively zero, after which the value is held constant for quantization. However, in practical circuits, achieving such an instantaneous sampling duration is impossible. Real-world implementations often require significantly longer time to sample the amplitude of the input signal, as depicted in Figure 2.
Figure 2, actual sampling scheme
Class D operation essentially involves sampling the input signal first and then "quantizing" it by determining the duty cycle of the PWM signal. The sampling process is illustrated in Figure 3.
Figure 3, sampling scheme of fix frequency class D AMP
It’s easy to observe that the sampling duration in a Class D amplifier is longer than in a typical sampling-and-hold scheme. As shown in Figure 4, a longer sampling duration introduces significant errors, which lead to noticeable distortion. Furthermore, the positive half of the signal waveform is sampled for a different duration than the negative half. This discrepancy results in significant even-order distortion.
Figure 4, errors caused by the long duration of sampling
Simulating Class D amplifiers is quite challenging, as the timing of the intersection point between the signal and the triangle wave can occur at any moment. Simulation tools like LTspice use fixed time steps, making it impossible to precisely locate the crosspoint, which results in inaccurate simulation results.
To address this issue, we need to resolve each intersection point to determine the correct timing. I’ve developed a Python program to solve this problem. The program is shared at the end of this thread, so if you're interested, feel free to experiment with it.
Figure 5 below shows the discretely constructed signal, where the triangle wave frequency is 15 times that of the sine wave. Figure 6 demonstrates that the full-bridge output stage can effectively cancel out the even order of harmonics. In contrast, Figure 7 shows that there is no distortion in the reconstructed signal when using traditional ideal sampling.
Figure 5, Constructed discrete sine wave of PWM modulation and its spectrum
Figure 6, Spectrum of the full bridge output of PWM modulation
Figure 7, Constructed discrete sine wave of ideal sampling and its spectrum
The following figures illustrate the second and third harmonic distortions of a 20kHz signal versus modulation frequency. Several conclusions can be drawn from the data:
Your suggestions and feedback are greatly appreciated. It’s possible that there are currently unknown issues with the simulation that could lead to inaccurate results. Therefore, I kindly advise you to interpret the simulation results with caution.
Figure 8, Second harmonic distortion with 0.2 modulation depth
Figure 9, Third harmonic distortion with 0.2 modulation depth
Figure 10, Second harmonic distortion with 0.4 modulation depth
Figure 11, Third harmonic distortion with 0.4 modulation depth
Figure 12, Second harmonic distortion with 0.8 modulation depth
Figure 13, Third harmonic distortion with 0.8 modulation depth
import numpy as np
from scipy.optimize import fsolve
import matplotlib.pyplot as plt
from numpy.fft import fft
D = 0.8 # modulation depth
M = 200 #number of periods
if False:
N = 15
freqOfSine = 1000
freqOfTria = N * freqOfSine
DeltaT = 1 / (2 * freqOfTria)
result_cross = np.zeros(2 * M * N + 2)
result_cross_n = np.zeros(2 * M * N + 2)
result_sampl = np.zeros(2 * M * N + 2)
def func_odd(t):
return -2 * (t % DeltaT) / DeltaT - D * np.sin(2 * np.pi * freqOfSine * t) + 1
def func_even(t):
return +2 * (t % DeltaT) / DeltaT - D * np.sin(2 * np.pi * freqOfSine * t) - 1
for i in range(int(2 * M * N) + 2):
# the definition domain is from i*DeltaT to (i+1)*DeltaT
# the triangle function is:
# y = -(2/DeltaT)*(t%DeltaT) + 1, when i is odd
# y = +(2/DeltaT)*(t%DeltaT) - 1, when i is even
# the sine wave function is:
# y = sin(2*pi*freqOfsine*t)
# the traditional sampling value is sin(2*pi*freqOfsine*(i+1)*DeltaT)
if i % 2 == 0:
result_cross = fsolve(func_even, (i + 0.5) * DeltaT)
result_cross_n = fsolve(func_odd, (i + 0.5) * DeltaT)
else:
result_cross = fsolve(func_odd, (i + 0.5) * DeltaT)
result_cross_n = fsolve(func_even, (i + 0.5) * DeltaT)
result_sampl = np.sin(2 * np.pi * freqOfSine * (i * DeltaT))
# print("cross results is:", result_cross)
# calculate the duty cycle
duty_cycle = np.zeros(M * N)
duty_cycle_n = np.zeros(M * N)
for i in range(M * N):
duty_cycle = (result_cross[2 * i + 1] - result_cross[2 * i]) / (
result_cross[2 * (i + 1)] - result_cross[2 * i]) - 0.5
duty_cycle_n = (result_cross_n[2 * i + 1] - result_cross_n[2 * i]) / (
result_cross_n[2 * (i + 1)] - result_cross_n[2 * i]) - 0.5
PLT_PWM = True
if PLT_PWM:
plt.plot(duty_cycle[0:3 * N], '-*')
plt.plot(duty_cycle_n[0:3 * N], '-*')
else:
plt.plot(-1*result_sampl[1:2*M*N:2][0:3 * N], '-*')
plt.show()
FULL_BRIDGE = True
if FULL_BRIDGE == True:
pwm_out = duty_cycle - duty_cycle_n
else:
pwm_out = duty_cycle
org_sap = -1 * result_sampl[1:2 * M * N:2]
pwm_out_freq = abs(fft(pwm_out))
print("the ratio is in dB:", 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[400]),
20 * np.log10(pwm_out_freq[200] / pwm_out_freq[600]), 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[800]),
20 * np.log10(pwm_out_freq[200] / pwm_out_freq[1000]))
print("")
if PLT_PWM:
plt.plot(20 * np.log10(pwm_out_freq)[0:1000])
else:
plt.plot(20*np.log10(abs(fft(org_sap)[0:1000])))
plt.show()
def func_odd(t, DeltaT, freqOfSine):
return -2*(t % DeltaT)/DeltaT - D*np.sin(2*np.pi*freqOfSine*t) + 1# - 0.4*np.sin(2*np.pi*0.9*freqOfSine*t)
def func_even(t, DeltaT, freqOfSine):
return +2*(t % DeltaT)/DeltaT - D*np.sin(2*np.pi*freqOfSine*t) - 1# - 0.4*np.sin(2*np.pi*0.9*freqOfSine*t)
def resolve(N): # times of the triangle frequency to that of the signal
freqOfSine = 1000
freqOfTria = N * freqOfSine
DeltaT = 1 / (2 * freqOfTria)
result_cross = np.zeros(2 * M * N + 2)
result_cross_n = np.zeros(2 * M * N + 2)
result_sampl = np.zeros(2 * M * N + 2)
for i in range(int(2 * M * N) + 2):
# the definition domain is from i*DeltaT to (i+1)*DeltaT
# the triangle function is:
# y = -(2/DeltaT)*(t%DeltaT) + 1, when i is odd
# y = +(2/DeltaT)*(t%DeltaT) - 1, when i is even
# the sine wave function is:
# y = sin(2*pi*freqOfsine*t)
# the traditional sampling value is sin(2*pi*freqOfsine*(i+1)*DeltaT)
if i % 2 == 0:
result_cross = fsolve(func_even, (i + 0.5) * DeltaT, args= (DeltaT, freqOfSine))
result_cross_n = fsolve(func_odd, (i + 0.5) * DeltaT, args= (DeltaT, freqOfSine))
else:
result_cross = fsolve(func_odd, (i + 0.5) * DeltaT, args= (DeltaT, freqOfSine))
result_cross_n = fsolve(func_even, (i + 0.5) * DeltaT, args= (DeltaT, freqOfSine))
result_sampl = np.sin(2 * np.pi * freqOfSine * (i * DeltaT))
duty_cycle = np.zeros(M * N)
duty_cycle_n = np.zeros(M * N)
for i in range(M * N):
duty_cycle = (result_cross[2 * i + 1] - result_cross[2 * i]) / (
result_cross[2 * (i + 1)] - result_cross[2 * i]) - 0.5
duty_cycle_n = (result_cross_n[2 * i + 1] - result_cross_n[2 * i]) / (
result_cross_n[2 * (i + 1)] - result_cross_n[2 * i]) - 0.5
pwm_out = duty_cycle
pwm_out_freq = abs(fft(pwm_out))
return 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[400]), 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[600]), 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[800]), 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[1000])
dist = np.zeros((34,4))
for i in range(34):
dist = resolve(15+i*5)
print(dist)
plt.plot(20 * np.arange(15, 185, 5), 100/10*(dist[:,0]/20), '')
plt.yscale('log')
plt.minorticks_on()
plt.grid(which='major', color='black', linestyle='-', linewidth=0.7)
plt.grid(which='minor', color='gray', linestyle=':', linewidth=0.5)
plt.xlabel("kHz")
plt.ylabel("Distortion(%)")
plt.title("Second harmonic distortion")
plt.show()
plt.plot(20 * np.arange(15, 185, 5), 100/10*(dist[:,1]/20), '')
plt.yscale('log')
plt.minorticks_on()
plt.grid(which='major', color='black', linestyle='-', linewidth=0.7)
plt.grid(which='minor', color='gray', linestyle=':', linewidth=0.5)
plt.xlabel("kHz")
plt.ylabel("Distortion(%)")
plt.title("Third harmonic distortion")
plt.show()
When considering the optimal operating frequency for a Class D amplifier, two contrasting ideas often emerge:
- According to Nyquist's theorem, 40 kHz should suffice.
- Based on DSD64 signals, 2.8 MHz appears to be adequate.
The diagram below illustrates the ideal sampling-and-hold process. In this scenario, the sampling time is effectively zero, after which the value is held constant for quantization. However, in practical circuits, achieving such an instantaneous sampling duration is impossible. Real-world implementations often require significantly longer time to sample the amplitude of the input signal, as depicted in Figure 2.
Figure 1, ideal sampling scheme
Figure 2, actual sampling scheme
Class D operation essentially involves sampling the input signal first and then "quantizing" it by determining the duty cycle of the PWM signal. The sampling process is illustrated in Figure 3.
Figure 3, sampling scheme of fix frequency class D AMP
It’s easy to observe that the sampling duration in a Class D amplifier is longer than in a typical sampling-and-hold scheme. As shown in Figure 4, a longer sampling duration introduces significant errors, which lead to noticeable distortion. Furthermore, the positive half of the signal waveform is sampled for a different duration than the negative half. This discrepancy results in significant even-order distortion.
Figure 4, errors caused by the long duration of sampling
Simulating Class D amplifiers is quite challenging, as the timing of the intersection point between the signal and the triangle wave can occur at any moment. Simulation tools like LTspice use fixed time steps, making it impossible to precisely locate the crosspoint, which results in inaccurate simulation results.
To address this issue, we need to resolve each intersection point to determine the correct timing. I’ve developed a Python program to solve this problem. The program is shared at the end of this thread, so if you're interested, feel free to experiment with it.
Figure 5 below shows the discretely constructed signal, where the triangle wave frequency is 15 times that of the sine wave. Figure 6 demonstrates that the full-bridge output stage can effectively cancel out the even order of harmonics. In contrast, Figure 7 shows that there is no distortion in the reconstructed signal when using traditional ideal sampling.
Figure 5, Constructed discrete sine wave of PWM modulation and its spectrum
Figure 6, Spectrum of the full bridge output of PWM modulation
Figure 7, Constructed discrete sine wave of ideal sampling and its spectrum
The following figures illustrate the second and third harmonic distortions of a 20kHz signal versus modulation frequency. Several conclusions can be drawn from the data:
- Second harmonic distortion is significant.
- Higher modulation frequency results in lower distortion.
- Lower modulation depth leads to lower distortion.
- A full-bridge output stage is essential.
- As shown in Figure 13, a modulation frequency of 3 MHz can achieve a third harmonic total harmonic distortion (THD) of 0.001% with a modulation depth of 0.8.
- If possible, use a smaller modulation depth. For example, the first headphone amplifier project employs a very low modulation depth with a power supply in the range of 9–12V.
Your suggestions and feedback are greatly appreciated. It’s possible that there are currently unknown issues with the simulation that could lead to inaccurate results. Therefore, I kindly advise you to interpret the simulation results with caution.
Figure 8, Second harmonic distortion with 0.2 modulation depth
Figure 9, Third harmonic distortion with 0.2 modulation depth
Figure 10, Second harmonic distortion with 0.4 modulation depth
Figure 11, Third harmonic distortion with 0.4 modulation depth
Figure 12, Second harmonic distortion with 0.8 modulation depth
Figure 13, Third harmonic distortion with 0.8 modulation depth
###########################################################################################################import numpy as np
from scipy.optimize import fsolve
import matplotlib.pyplot as plt
from numpy.fft import fft
D = 0.8 # modulation depth
M = 200 #number of periods
if False:
N = 15
freqOfSine = 1000
freqOfTria = N * freqOfSine
DeltaT = 1 / (2 * freqOfTria)
result_cross = np.zeros(2 * M * N + 2)
result_cross_n = np.zeros(2 * M * N + 2)
result_sampl = np.zeros(2 * M * N + 2)
def func_odd(t):
return -2 * (t % DeltaT) / DeltaT - D * np.sin(2 * np.pi * freqOfSine * t) + 1
def func_even(t):
return +2 * (t % DeltaT) / DeltaT - D * np.sin(2 * np.pi * freqOfSine * t) - 1
for i in range(int(2 * M * N) + 2):
# the definition domain is from i*DeltaT to (i+1)*DeltaT
# the triangle function is:
# y = -(2/DeltaT)*(t%DeltaT) + 1, when i is odd
# y = +(2/DeltaT)*(t%DeltaT) - 1, when i is even
# the sine wave function is:
# y = sin(2*pi*freqOfsine*t)
# the traditional sampling value is sin(2*pi*freqOfsine*(i+1)*DeltaT)
if i % 2 == 0:
result_cross = fsolve(func_even, (i + 0.5) * DeltaT)
result_cross_n = fsolve(func_odd, (i + 0.5) * DeltaT)
else:
result_cross = fsolve(func_odd, (i + 0.5) * DeltaT)
result_cross_n = fsolve(func_even, (i + 0.5) * DeltaT)
result_sampl = np.sin(2 * np.pi * freqOfSine * (i * DeltaT))
# print("cross results is:", result_cross)
# calculate the duty cycle
duty_cycle = np.zeros(M * N)
duty_cycle_n = np.zeros(M * N)
for i in range(M * N):
duty_cycle = (result_cross[2 * i + 1] - result_cross[2 * i]) / (
result_cross[2 * (i + 1)] - result_cross[2 * i]) - 0.5
duty_cycle_n = (result_cross_n[2 * i + 1] - result_cross_n[2 * i]) / (
result_cross_n[2 * (i + 1)] - result_cross_n[2 * i]) - 0.5
PLT_PWM = True
if PLT_PWM:
plt.plot(duty_cycle[0:3 * N], '-*')
plt.plot(duty_cycle_n[0:3 * N], '-*')
else:
plt.plot(-1*result_sampl[1:2*M*N:2][0:3 * N], '-*')
plt.show()
FULL_BRIDGE = True
if FULL_BRIDGE == True:
pwm_out = duty_cycle - duty_cycle_n
else:
pwm_out = duty_cycle
org_sap = -1 * result_sampl[1:2 * M * N:2]
pwm_out_freq = abs(fft(pwm_out))
print("the ratio is in dB:", 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[400]),
20 * np.log10(pwm_out_freq[200] / pwm_out_freq[600]), 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[800]),
20 * np.log10(pwm_out_freq[200] / pwm_out_freq[1000]))
print("")
if PLT_PWM:
plt.plot(20 * np.log10(pwm_out_freq)[0:1000])
else:
plt.plot(20*np.log10(abs(fft(org_sap)[0:1000])))
plt.show()
def func_odd(t, DeltaT, freqOfSine):
return -2*(t % DeltaT)/DeltaT - D*np.sin(2*np.pi*freqOfSine*t) + 1# - 0.4*np.sin(2*np.pi*0.9*freqOfSine*t)
def func_even(t, DeltaT, freqOfSine):
return +2*(t % DeltaT)/DeltaT - D*np.sin(2*np.pi*freqOfSine*t) - 1# - 0.4*np.sin(2*np.pi*0.9*freqOfSine*t)
def resolve(N): # times of the triangle frequency to that of the signal
freqOfSine = 1000
freqOfTria = N * freqOfSine
DeltaT = 1 / (2 * freqOfTria)
result_cross = np.zeros(2 * M * N + 2)
result_cross_n = np.zeros(2 * M * N + 2)
result_sampl = np.zeros(2 * M * N + 2)
for i in range(int(2 * M * N) + 2):
# the definition domain is from i*DeltaT to (i+1)*DeltaT
# the triangle function is:
# y = -(2/DeltaT)*(t%DeltaT) + 1, when i is odd
# y = +(2/DeltaT)*(t%DeltaT) - 1, when i is even
# the sine wave function is:
# y = sin(2*pi*freqOfsine*t)
# the traditional sampling value is sin(2*pi*freqOfsine*(i+1)*DeltaT)
if i % 2 == 0:
result_cross = fsolve(func_even, (i + 0.5) * DeltaT, args= (DeltaT, freqOfSine))
result_cross_n = fsolve(func_odd, (i + 0.5) * DeltaT, args= (DeltaT, freqOfSine))
else:
result_cross = fsolve(func_odd, (i + 0.5) * DeltaT, args= (DeltaT, freqOfSine))
result_cross_n = fsolve(func_even, (i + 0.5) * DeltaT, args= (DeltaT, freqOfSine))
result_sampl = np.sin(2 * np.pi * freqOfSine * (i * DeltaT))
duty_cycle = np.zeros(M * N)
duty_cycle_n = np.zeros(M * N)
for i in range(M * N):
duty_cycle = (result_cross[2 * i + 1] - result_cross[2 * i]) / (
result_cross[2 * (i + 1)] - result_cross[2 * i]) - 0.5
duty_cycle_n = (result_cross_n[2 * i + 1] - result_cross_n[2 * i]) / (
result_cross_n[2 * (i + 1)] - result_cross_n[2 * i]) - 0.5
pwm_out = duty_cycle
pwm_out_freq = abs(fft(pwm_out))
return 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[400]), 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[600]), 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[800]), 20 * np.log10(pwm_out_freq[200] / pwm_out_freq[1000])
dist = np.zeros((34,4))
for i in range(34):
dist = resolve(15+i*5)
print(dist)
plt.plot(20 * np.arange(15, 185, 5), 100/10*(dist[:,0]/20), '')
plt.yscale('log')
plt.minorticks_on()
plt.grid(which='major', color='black', linestyle='-', linewidth=0.7)
plt.grid(which='minor', color='gray', linestyle=':', linewidth=0.5)
plt.xlabel("kHz")
plt.ylabel("Distortion(%)")
plt.title("Second harmonic distortion")
plt.show()
plt.plot(20 * np.arange(15, 185, 5), 100/10*(dist[:,1]/20), '')
plt.yscale('log')
plt.minorticks_on()
plt.grid(which='major', color='black', linestyle='-', linewidth=0.7)
plt.grid(which='minor', color='gray', linestyle=':', linewidth=0.5)
plt.xlabel("kHz")
plt.ylabel("Distortion(%)")
plt.title("Third harmonic distortion")
plt.show()