I’m not suggesting losing the local caps - I often use them. Or going fully differential. But just watch the grounding. Connect clean ground to clean ground, dirty ground to dirty ground, and connect those two separately to the center tap of the trafo. Boards for individual channels need to be designed with that in mind, rather than just having a single “ground” lug. The two clean grounds of course need to be as physically close to one another as possible. I like to stack PCBs, and have a spade lug on both sides. That makes a very short connection between the two clean grounds.
Connecting C4 and R2 to "PWRGND" is troubling. I would use a separate wire to the PS for all "input" grounds, or better said, avoid any supply or output currents in the input ground system. I would collect all input grounds, including the input jacks together before they connect to supply ground.
I reduced the capacitance to 220uF plus 100nF in parallel. That seems in line with what Self and Elliott use in their designs. I thought having a lot of energy right next to the output devices would be beneficial, but I buy your argument about potential imbalance between the channels.
The version in post 123 has dramatically improved from earlier renditions. In my simulations on LT SPICE I am impressed by the performance of the devices selected. We can tip our hats to D.Self and the gang at DIYAudio for another classic ampliifer. njswede you really did it. You'll have to change the name to ABOG. A for above. Aha...cheers.
Point taken. I’ll leave C4 and R2 in the layout so I can experiment and compare both methods.
I'll just say, well write, that this is a great thread: constructive, collaborative and informative. I'll be interested in boards, or gerbers, or whatever when the design is finalized. Kudos to all who participated.
I've been reading with interest.
Voltage across C8 and R23 is only loosely tied to Q7, and would vary according to the whims of the -0.02V/°C tempco of the drivers. Perhaps there are some PNP-NPN pairs that can be bought integrated, for better thermal coupling? In any case, the VAS / bias / driver section doesn't quite make sense. Maybe the Q7 section could be moved between the driver emitters?
The Vbe of Q7 is multiplied by the divider r11, R12+VR1 and tracks the driver Vbe's (2x0.65V) plus the OP Vto (2x~4V) ~= 9.3V. As I said before, Q14 is upside down in post #123. This is "bog standard". The drivers will provide whatever current was required to follow the voltage from Q7, so another Vbe multiplier there would be useless. Without Q7 where it is, the drivers would burn up. This is all standard "blameless" topology, which I suggest you study to better understand.
No problem! What's the purpose of C8, then? At first glance it looks like it's for common-mode ripple rejection, but:
1 / (2pi × 680 × 0.00000022)
gives a rather tame 1063 Hz or so corner frequency. Why not get rid of it altogether? C6 is already there, right?
Or make C8 a higher value like 10uF? But then why double up on C6 in the first place?
Would that give the amplifier a more dramatic sound?
C8 is a so-called "speed-up cap".
It reduces transistor switching time and improves the transient response - you can observe it as faster rise time when testing with square waves.
Helps speed up the charge and discharge of the transistors base capacitance.
BJT usually amps use values 1uF - 2.2uF; for mosfet amps 100nF - 220nF is enough.
It reduces transistor switching time and improves the transient response - you can observe it as faster rise time when testing with square waves.
Helps speed up the charge and discharge of the transistors base capacitance.
BJT usually amps use values 1uF - 2.2uF; for mosfet amps 100nF - 220nF is enough.
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C8 just needs to store/absorb more charge than the gates or bases of the output transistors. So it’s voltage doesn’t change as it sucks up the gate charge at turn off. ESR doesn’t need to be spectacularly low when used for mosfets, because the gate stopper limits how fast charge can be sucked out anyway. With bipolars, the lower the AC resistance in that path the better off you are - especially for minimizing cross conduction with square waves. Bipolars turn off slower than they turn on, and every little bit helps.
Does it mean that for IRFPs 10nF - 20nF would be enough?
In the simulations 100-220 nF seemed optimal...
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By “more charge”, a factor of 10+. Just like when doing a boot strap cap for driving a high side switch.
It's important to understand that while MOSFET have a high DC input impedance, they have a substantial input capacitance, especially the "Miller" capacitance from gate to drain, which is multiplied by the Drain-Source voltage slew involved, similar to a "capacitance multiplier". Without C7, gate current from the opposite driver has a (680+47)/47 ~=15.5 times slower time constant which means the FET coming on is much quicker than the FET going off which creates a shoot-through current surge on every zero crossing. The same thing applies to BJT transistors and in years past (hopefully) driving a solid-state amp at high power above 10KHz would cause it to self-destruct.
The asymmetry and multitude of signal paths just doesn't look right. Could C8 + R23 then be moved to the other side of the gate stoppers? They would double as emitter resistors, making the drivers' current-sinking and sourcing more symmetrical (with less distortion from dynamic P = Vce * I changes) and C8 no longer has 94 ohms of ESR added. If that's too unstable, perhaps separate emitter resistors could be added?
I understand that - I wasn't suggesting to delete it altogether from its original position. It's just that C8 and R23 seem to replicate its core functionality on the output side of the drivers.
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I understand that - I wasn't suggesting to delete it altogether from its original position. It's just that C8 and R23 seem to replicate its core functionality on the output side of the drivers.