For every single type of dac architecture?
How do you personally define a 'poor' oscillator as verses a 'good' one, in terms of close-in phase noise measurements?
Is your 'conclusion' merely an opinion stated as if it were fact?
Please sir, live up to your own standards as you would like to see other people do.
One aside, if I may: For all the many people who have compared listening to Crystek, Accusilicon, and or NDK SDA clocks in some board that allows it, such as FIFO_Pi, they all sound pretty awful, with Accusilicon usually coming out as preferred. Those same people may find plugging in one of Andrea's clocks provides a dramatic improvement is SQ.
I have put off probably for too long talking about my findings and thoughts on that. The biggest problem is almost certainly with Ian's clocking implementation. Is how the clocks are powered, bypassed, buffered, etc. Andrea's clocks are separately powered, well implemented, and well buffered before going into FIFO_Pi.
Ian measures jitter with a scope jitter measurement package, not a time pod or similar instrumentation that is specifically for close-in phase noise.
Anyone's guess if any of the other measurement-oriented guys are doing better or worse relative to Ian.
The above thoughts are all I am going to share on the subject for now.
I have put off probably for too long talking about my findings and thoughts on that. The biggest problem is almost certainly with Ian's clocking implementation. Is how the clocks are powered, bypassed, buffered, etc. Andrea's clocks are separately powered, well implemented, and well buffered before going into FIFO_Pi.
Ian measures jitter with a scope jitter measurement package, not a time pod or similar instrumentation that is specifically for close-in phase noise.
Anyone's guess if any of the other measurement-oriented guys are doing better or worse relative to Ian.
The above thoughts are all I am going to share on the subject for now.
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I have measured NDK SDA clocks, Crystek CCHD, Andrea's clocks and some else. These are distributed in the Well Tempered.. thread. The difference is significant, in the close-in (1Hz ) zone between all the other clocks <> Andrea's
The Accusilicon clock I only have in my Topping dac, and did not want to massacre.. it's 45/49MHz but that is not a problem
Thanks, for that clarification, Marcel. Many years ago, one of the projects I was involved with was the development of a digital cordless telephone chipset. The part of the team working on the frequency-hopping radio would always talk in terms of link ENOB for, as you indicate, link error budgeting. I didn’t know too much about digital radio links, so it was then that I started the habit of sometimes improperly referring to signal domain conversion SINAD losses generally, in terms of ENOB.
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Were they mainly using delta-sigma DACs?
Is there a guide to the interplay between ENOB and linearity?
I implemented NDK SDA with its own power supply separate from Ian's FIFOPi and changed out his ceramic caps, added a supercap and a BG HiQ and sound was substantially better than NDK simply plugged into Ian's PCB. Then replaced NDK first with Andrea's gen1 drisco and it was clearly better than my NDK efforts. Upgrading to his 5MHz current Drisco brought a small but worthwhile improvement particularly with ReclockPi & SinePi.
RyanJ 1541a pcb, dual mono triode output Fikus style, Ian FifoPi stack, WellAudio 5MHz clock. CLC power supplies with supercaps & BlackGates.
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thanks @Markw4 for your sharing. I have done about the same tests, I add that I have also tried new class d neutrino and ns2. I have always preferred accusilicon until I mounted andrea's clocks. I believe that real audio is studying, rehearsing, listening and discussing. no studying and giving judgments without having tried or heard.
Those who claim that low close-in phase noise is of utmost importance have not made any exceptions between DAC architectures so why should it be different if an opposite claim is made? According to your listening tests close-in phase noise is not that important for DACs used in your tests (DS & R2R).
Ask Andrea who claimed that Crystek 957 is a poor oscillator.
My conclusion was based on evidence provided by you and Andrea. Maybe you can provide an alternative conclusion based on the same evidence.
Close-in phase noise is a property of the crystal. Ancillary circuitry mainly impacts far out noise floor. So if proper clocking implementation mitigates the issues of higher close-in phase noise then it just confirms that low close-in phase noise is not that important.
Do you mean property of the crystal oscillator? It's not just the crystal determining the close-in phase noise, also the rest of the oscillator.
just wanted to say that (the crystal defines the reachable limits, but the oscillator can spoil that)
Yes, I should have said crystal oscillator. Anyhow the close-in phase noise of Crystek 957 is what it is. The ancillary circuitry does little to improve it.
The ancillary circuitry can introduce heavy spurious contamination, (line noise, data correlated jitter etc)
I agree. I have never said that clocking implementation is not important. I just commented on the importance of close-in phase noise.
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