T-network: the better feedback solution?

[theChris]

i've built one of these amps last year. i had a post about it but no pics. i called it the HI3GC -- high input impedance inverting gainclone.

used as a woofer amp.

pros to design:
1.) small feedback cap.
2.) stable, it worked fine.

cons:
1.) increased DC offset (70mV for what should be equal input biases). this was on a bridged design, but the dc offset was overall higher then the non-HI3GC
2.) more parts
3.) you can get more dependence on tolerances.

this was on a lm4780, so i'd suspect chip difference should have been low...

 

[carlosfm]

this was on a lm4780, so i'd suspect chip difference should have been low...

The difference in DC-offset between the two channels of this chip is very low.
After all, it's a 2-channel chip.
But the resulting DC-offset still varies from chip to chip.

 

[carlosfm]

...so other WILL convert to T-Network. [/B]

I will try it.
With valve buffer.

 

[Joe Rasmussen]

Hello Joe,

....This practically means that the initial offset after the first resistor is amplified by the factor of 101.

Pedja

Yes indeed, it seems that changing this ratio is desirable, to say around 50:1 or even a little lower, like 46:1. I am going to try the following:

If retaining that 10K but increasing 100R to 220R (staying with standard values), now increase the other 10K to 22K, retain the 22K input Z (or similarly 18K + 4K7 with the standard tube buffer with LPF), then 22K on (+) input to ground. This should pretty much halve the potential DC Offset so that rarely should go higher than 25mV? Should work.

This will remove further any need to null, and besides nulling is not desirable in Terry's view and I'm coming around to that view as well. For other DIY'ourselfers who wish to assemble this, or update their amps to T-Network, we need to guide them and give them a set of fixed values that works.

So my revised suggestion is, 22K input Z, then 22K to 220R which is grounded, then to 10K to output, Matching 22K on (+) is 1% near ideal target 22K2. Gain is in the mid-fourties.

The ideal 22K2 results from 10K/220R in parallel = 218R plus 22K in series = 22K2 rounded.

This will balance both 'R' and 'C' and reasonably low DC Offset.

I will also post a revised schematic so the above will be clearer for everyone.

Joe R.

 

[Joe Rasmussen]

Yikes!

That didn't work out, went from +38mV to +52mV - back to the drawing board - in the meantime stay with earlier values.

 

[theChris]

The difference in DC-offset between the two channels of this chip is very low.
After all, it's a 2-channel chip.
But the resulting DC-offset still varies from chip to chip.

i meant that the DC offset couldn't be easily attributed to "chip to chip" issues becuase the chips were integrated together. i know 1 channel had 20mV alone, and combined it came to 70mV...

i'mm have to go home and find out what resistors i used. i think there was a 330 ohm in there somewhere. i remeber the values all lines up fairly well.

 

[Nuuk]

He also feels that since R and C (or DC and AC) Z paths are more important and should both be the same, so live with the Offset of less than 50mV, don't null the DC. So it may well sound better if left un-nulled.

I have always found (and reported) with the IGC (using a single feedback resistor), that it sounds better to me when I accept the DC offset not being zero and don't try and null it with the resistor from non-inverting to ground.

The best sounding IGC I have has DC offset of around 50mV on one channel and around 30mV on the other.

Full marks to Joe for trying to make this available to those of us without the technical understanding, a policy that I have always tried to adhere to with Decibel Dungeon. I for one, greatly appreciate his attitude!

"IT IS THE FRUIT THAT MAKES THE TREE BOW LOW."

 

[Joe Rasmussen]

OK, while many of our Euro Brethren still have their heads on pillows, I have been a busy bee.

I now know why the last one blew out from 38mV to 52mV. This particular chip has significant more Input Offset current - so increasing to 22K that became the dominant factor.

Let's examine four different chips:

One:

(+) Input Current = 0.105uA

(-) Input Current = 0.150uA

Input Offset Current = 0.045uA **** very high - not within spec

Input Offset Voltage = 3.1mV **** not typical

DC Offset = 38mV


Two:

(+) Input Current = 0.080uA

(-) Input Current = 0.072uA

Input Offset Current = 0.008uA **** very good

Input Offset Voltage = 0.1mV

DC Offset = 8mV


Three:

(+) Input Current = 0.080uA

(-) Input Current = 0.080uA

Input Offset Current = zero **** perfect

Input Offset Voltage = 0.1mV

DC Offset = 6mV


Four:

(+) Input Current = 0.100uA

(-) Input Current = 0.080uA

Input Offset Current = 0.020uA

Input Offset Voltage = 0.5mV

DC Offset = 26mV

Look at the data sheeet One is not within spec on Input Offset current, and 3.1mV Offset voltage is not typical (1mV) but within max (10mV). I say this because I believe One is not typical overall.

All above vere 10K/100R/10K & 10K on (+).

Now changing this to 22K/220R/10K (on output) & 22K on (+), got the following result:

One: Went up from 38mV to 52mV - affected by Input Offset Current and voltage - but more suspicion re current.

Two: Went down from 8mV to 4mV - the reduction because Offset current is low. So is Offset voltage.

So using 10K/100R/10K & 10K on (+), is better able to deal with Input Offset current. Whereas 22K/220R/10K (on output) & 22K reduces DC Offset on the main output only if Input Offset current is reasonable or typical.

There there is a point where going for better than 100:1 ratio down to 46:1 ratio ought to be better and usually is, but in the, hopefully only occasional chip, the imbalance in the input currents swamps the advantage because we end up using 22K - the higher Z becomes a disadvantage.

WHEW!

Wake up guys... awaiting feedback.

Joe R.

 

[Joe Rasmussen]

Full marks to Joe...

Hey Nick, I will make you president of my fan club...

Seriously, while I think of it, I also want to thank Terry Demol for picking his brains.

Joe R.

 

[Nuuk]

I'm awake and listening Joe (I am still partly on Laverton time despite the 24 year gap ).

For a newbie, how do you measure the chip to see if it is within spec? Is it as simple as placing a meter in series with each input and reading the current?

 

[bigparsnip]

Well, I forgot to get the link at work the other day and it seems people have been buisy in my absence (which is always interesting). anyway, I have included the link to the application note below for those who are interested, and although it is technicaly describing transimpedance amplifiers, you only need and one extra resistor to the circuit to get you NIGC configuration.

http://focus.ti.com/lit/an/sboa060/sboa060.pdf

 

[Joe Rasmussen]

...how do you measure the chip to see if it is within spec? Is it as simple as placing a meter in series with each input and reading the current?

It's not as difficult as might seem. In your current VIGC, measure the voltage across the 1M from (+) to ground. This will be in mV, now devide that by 1000000 (1M). This in Amps is the Input (also called Bias) current. The typical seems to be 0.0000001A or 0.1uA or 100pA.

Example: You read 1.2mV, then 0.0012 devide 1000000 = 0.0000000012A or 1.2uA or 120pA.

Next you do exactly the same across the other 1M connected from (-) input to output pin. This is now the (-) Input (Bias) current. Ideally they should measure exactly the same, if they do you will have zero Input Offset current. The latter is the difference between the two. So if you have 120pA on one and 100pA on the other, the offset is 20pA. or 0.020uA

Finally the Input Offset voltage is the voltage across (+) and (-) in mV.

Knowing this, you can do what I did and post the results here. The perfect chip will have the same input current (balanced) and hence zero offset current. It will also have zero voltage across (+) and (-) pins/inputs. A chip like that would also have zero DC Offset on the output if the R values are the same, whether 1M or whatever. Is there one out there? Well, we can all dream.

Have a go.

Joe R.

 

[carlosfm]

It would be nice to match two chips before using them on a circuit...

 

[Joe Rasmussen]

It would be nice to match two chips before using them on a circuit...

Do I hear a business proposal?

 

[Circlotron]

I had a related experience in a feedback cct not on a GainClone but a single mosfet x10 voltage amplifying stage. Initially I had a feedback resistor of 3M3 and an input resistor of 330k. It worked but wasn't great. *BIG* improvement when I reduced both resistors by a factor of 10. Seems the nonlinear gate capacitance with signal voltage was making a visually noticeable amount of distortion on the 'scope.

The voltage swing on the virtual earth summing junction, the "-" input of a chip amp would be very low by comparison with my mosfet gate, but you never know...

 

[diy_audio_fo]

I think people here may have some misconception about the use of a high value resisstor as the feedback element for an op-amp (or in this case a chip amp).

What you may acheive is reducing the size of the feedback resistor being used when you use a t-network for a similar gain/input impedance combination.

This may give the apearance of two benifits to your circuit design:

one: the lower feedback resistance will alow a higher bandwidth in extreem cases where parasitic capacitances are causing band limiting of the circuit. However, at audio frequencies I doubt that this should ever become a real problem which can't be solved with proper PCB design and circuit layout.

two: this is probably the one which people will talk about the most (but isn't actualy a real benifit, but leads to poorer performance), that the lower value resistors that you are now using in your feedback network are of lower values than before and so will contribute lower noise into the signal path. BUT, what is actualy the case here is that the t-network will lead to a lower overall noise performance for the circuit once you consider it as a whole. This happens because, as you increse the feedback resistor's value, you will be increasing the amount of noise it creates by a factor proportional to the square root of the increase in value (increase the vallue of resistor by a factor of four and the noise voltage it creates will go up by a factor of two).

However, what most people will forget, is that whilst the noise is increasing, you are also increasing the gain of the device,

so proportinately, the output signal will be getting larger compared to the noise you are creating by using the larger resistor (so in efect, due to noise goin up by a factor proportional to the square of the increace, and the output going up by a factor exactly proportional to the increace, the SNR will actualy be improved by a factor proportional to the square root of the increace in feedback resistor value).

Therefore, in this case (as with many others) it will always be better to use a single high value feedback resistor in place of a t-network (these are only of use in two situations, firstly if you can't get hold of resistors of suficiently high values; and secondly, if you need to increace the speed of the amplifier feedback and are willing to acrifice some SNR performanceto do so) when desiging the feedback around an inverting amplifier.

Anyway, I hope I haven't missed out too much here (I missed out the bit about noise gain when using the t-network, which means that you don't have the same increace in SNR performance as with a single resistor, but I could always try and explain further if people want, but there are some good data sheets on the ti website which cover the topic better than I can) and if people have questions I can try my best to answer.

Andrew.

http://focus.ti.com/lit/an/sboa060/sboa060.pdf


At a first glance you are OK, but, please think twice!

I've had your same think but I proved myself I was wrong. I already knew the AppNote

What you state is correct for transimpedance amplifier with a current at the input NOT for a voltage amplifier (inverting or non inverting).
In the case of voltage amplifier the voltage gain is proportional to the RATIO of two or more resistors NOT their absolute value. The noise instead is proportional to the square root of the value of the resistor.
So you maximize the signal to noise ratio (in voltage amplifier) lowering the absolute value of the resistors.

Hint: there is a very special case in which T feedback is NOT the best solution in voltage amplifier: do you guess?

 

[Pedja]

Look at the data sheeet One is not within spec on Input Offset current, and 3.1mV Offset voltage is not typical (1mV) but within max (10mV). I say this because I believe One is not typical overall.

Seems so.

So using 10K/100R/10K & 10K on (+), is better able to deal with Input Offset current. Whereas 22K/220R/10K (on output) & 22K reduces DC Offset on the main output only if Input Offset current is reasonable or typical.

Yes, with typical bias current and if the first resistor is higher than 10k, offset developed by the bias current will start to dominate over rather than it will null the contribution of the input offset voltage. So, I’d stop here at 10k.

I’d say the rest of feedback made of 100R and 10k, plus 22k series input, and 10k shunt at + input is fine both to keep relatively similar impedances at the inputs and modest DC offset.

These values may be good either for tube or solid state buffers or no buffers at all.

As a final result, I doubt the offset at the output will come higher than 50mV. Though it will vary below this point more than we accustomed to have using a conventional feedback. So, if it does, everything is under control.

Pedja

 

[Sheldon]

Not elegant, but if all else fails, or for out of spec chips, this can be done:

http://www.diyaudio.com/forums/showthread.php?postid=449317#post449317

Sheldon


Pedja, with a 22k input resistor, would you recalculate your LP recommendations or not?

 

[theChris]

It would be nice to match two chips before using them on a circuit...

you may concider using a lm4780 or 4732. it didn't work for me, but might for you.

 

[Pedja]

Pedja, with a 22k input resistor, would you recalculate your LP recommendations or not?

Hi Sheldon,

It is simlar to the NIGC. The impedance here is mainly determined by the first series resistor. This 22k instead of 10k will shift the slope a bit down, and to keep the previous slope you may use somewhat lower value for the first resistor. Something like 900R instead of 1k will be fine.

Pedja