Subjective effect of Baker clamps

Unfortunately, Michael Kiwanunka has the propensity to overcomplicate things and mix strong opinions with fact. Clamp diodes (and especially using fast modern devices) offer an elegant and trouble free way to deal with the problem of sticky rail and the concomitant high VAS currents. Cascodes that use emitter current limiting don't make things any better because you loose precious voltage swing.

Cordell is still the gold standard for solid, practical design advice.
 
You only need some capacitance and inductance and 180 degree phase shift across any two ports and you have the potential for oscillation - so its not just a simple case of negative resistance being reflected back into the base. Cordell discusses this in some general terms in his book where he talks about the Colpitts problem with followers. The small collector resistor acts to damp that, the same way a base stopper does.

This kind of reminds me of college, when the geeks used to stand around and have these high-faultin' arguments, and we would all be impressed with ourselves. 🙂 No offense intended, I'm just getting a little self-conscious.

An inductor in the collector lead, and a capacitor from collector to ground, and another capacitor from base to ground, a little negative base resistance, all in the right proportions, form a Colpitts oscillator. I don't know right now exactly why the emitter follower base resistance looks negative; maybe someone can find a link to a paper explaining it.

I would like to see a more rigorous analysis with small-signal circuit models to make all this clearer. I agree any transistor with the right stray reactances around it can potentially oscillate. I also know there are millions of amplifiers out there that don't have stopper resistors and they don't have parasitic local oscillations, either. Sometimes things work out, though seemingly not so much the past five years.

I haven't seen any evidence of such oscillation in either of my HPA amplifiers, neither cascodes nor emitter followers. I did have an oscillation in the DCG3 at high enough frequency that I think it might have been local to the output MOSFET. As we said earlier, the clipping instability I saw in HPA1 was almost certainly a global loop problem.

I try to design compact, intelligently laid-out PC boards. Like I said, I'm amazed the things work at all given my past history of building power oscillators.

You certainly know Kiwanunka's work better than I do. I appreciate the detail in his paper. As to his opinions, I don't see a word anywhere, nor in Self's work, nor Groner's, about sound quality.
 
I won't comment on dadod's approach but leave that to him to do other than to say his distortion performance shows no ill effects from using a high collector resistor to limit VAS peak current under clipping conditions.

That's exactly the problem. Of course, under closed loop ideal conditions, Vce is very small (as any other variable inside the feedback loop). It appears slightly larger for the CFA case, since the CFAs have in general lower loop gain.

The problem becomes critical when the output approaches the rails, both with the distortions and possibly the stability. If I remember correctly, Dadod's amplifiers all run at a generous supply voltage reserves, like +/-55V for an 100W amplifier, that's the core reasons why his amplifiers show a rather low distortion vs. output level variation, so no surprise for him there's very little concern.

Designing based on simulations only, following the happy path (ideal conditions), never worked for me. It is the corner cases (clipping behavior, worst case stability, etc...) that dictate the ultimate amplifier quality.

BTW, I am not sure how AKSA concluded the collector resistor in an emitter follower VAS buffer affects the slew rate, that's total nonsense. But I suspect we don't even agree on a common definition of "slew rate", so I'll leave it at this, for now.
 
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@hapsternsck I think it was determined your issue was not parasitic oscillation, but misbehavior in the clipping situation and that’s what you need to solve in your specific case.

I’ve explained to you the potential risks of parasitic oscillation. You do not need to take my word for it, just Google it.
 
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DIMn (using a 4:1 ratio of a square wave (fixed at 3.15 kHz) with a sine wave (fixed at 15 kHz) and the result filtered by a single pole LPF at n KHz) can also be used, it is a standard measurement in audio. It is much more sensitive to nonlinearities when approaching the rails than the simple sine measurement.

With the current stock device models, the case of entering hard limitations (clipping, etc...) is probably the worst use case for simulation.
 
@hapsternsck I think it was determined your issue was not parasitic oscillation, but misbehavior in the clipping situation and that’s what you need to solve in your specific case.

I’ve explained to you the potential risks of parasitic oscillation. You do not need to take my word for it, just Google it.

Thank you. I didn't mean to imply that parasitic oscillation doesn't happen. I'm just not interested in that aspect of the problem since it doesn't seem to apply here. I've read Cordell and done my Googling and haven't found anything useful about emitter follower collector resistors.

Your excellent page on anti-saturation diodes proposes three solutions to saturation, but doesn't explain the tradeoffs between them. I was surprised how badly the amplifier behaved with the limiter transistor, and how well the Baker clamp worked. My hunch is the limiter transistor action isn't sharp enough, and it puts the amplifier in a state of middling gain at the onset of clipping, compromising loop stability.

I've already explained several times why I'm suspicious of the otherwise marvelous Baker clamp and seek a different solution.

I wholeheartedly agree that SPICE simulations and small-signal models are almost useless here. It's a hard problem.

For what it's worth, I have papers in a drawer somewhere that say I have not one, but two electrical engineering degrees. I chose, maybe by mistake, to go into a career in software, so I don't pretend to be a real electrical engineer (but I play one on TV). I have enough background to drill down on this problem. After years of working on complex software systems, I've learned to be relentless when trying to understand and debug edge case failures. I am hoping some people may find my comments helpful, even while others may think, "STFU already."