Maybe.
Previously I had one full duplex device, and the PCM384 with I2S isolation had difficulties.
At that time, a high-speed USB isolator cost ~300-350 euros.
Now of course this is not a problem, thanks USBISO211 from TI and ADUM3165/66 (or 4165/66) from AD, I use both in my isolators.
Well, nobody is disputing this mode as all the I2S signals are skewed by the same amount. Skew of MCLK coming from the other direction is not important. I am talking about the mixed direction which is quite difficult to avoid in the duplex setup.
Of course I mean these recent low-cost options, I would not have advocated isolating USB HS instead of I2S three years ago 🙂
USB isolation alone does not solve all potential noise issues. This is why I use isolators for I2S/I2C/GPIO. Full-duplex mode is not really needed if ADC and DAC use the same MCK.
Please can you explain a bit? IIUC for the isolators delay to be unimportant all the three I2s signals must go in the same direction. That requires two independent I2S interfaces - one in master (with external mclk input), the other in slave. With two I2S interfaces DAC and ADC can run asynchronously, i.e. they could even have separatel mclks (e.g. SPDIF input and crystal-clocked DAC output). UAC2 async is independent for each direction.
What I mentioned, was not 3 but ~10 years ago 🙂
Since that time i used I2S isolation n ACD/DAC. I very rarely need them in one device, but it is possible.
One solutions just requires to double the isolators quantity. For example, the signals MCLK, WCLK, BCLK, ADCData come from the ADC to the controller through one ISO, and WCLK', BCLK' and DACData go to the DAC through another.
As I said on my boards I2S controller is the master for DAC and slave for ADC. I2S controller can use MCK from DAC, or from ADC, or from external clock (which can also be used for ADC). In the latter 2 cases (MCK from ADC or from external clock) DAC and ADC are synchronous.
Just to clarify, on my dacs there is no MCK but MCK resides on the I2S controller board or comes from external clock. As MCK on I2S controller board is isolated from I2S controller MCK is logically part of DAC and the MCK power supply comes from the DAC.
Thanks so much for sharing all those elements. I have read the discussion 3 times, learned things, understood that the topic is larger than I imagined... Good for learning... not so much for progressing on my design ;-)
Sometime it is difficult for me to be synthetic. Sorry.
I have to do my homework about ground loops, that I understand are sort of sure thing if doing meadurements on the DAC performance with ADC without precautions.I still have to understand why there are not common issues when PC + DAC + Amplifier each has his power supply and no isolation between those? Or how are done the Audioscience review tests, where I don't see often discussed isolators?
One thing I appreciate in design, that I could word as "system engineering" is understanding the functions and allocating those to the correct subsystems to achieve good performance with "measured" means. Prefering simple solutions when possible... I started with the idea of versatile multichannel USB to I2S bridge, for Hobbyists interested in things like CamillaDSP to control active speakers (or speakers + subwoofers).
That bridge should possibly be a good companion for good to very good DACS, which I assimilated to (but not be sufficient):
Not so simple...
As often, it can be more difficult to design a versatile component, able to cope with different intentions, than a dedicated one for an integrated design:
And I know that this is purely intellectual, as the first target is a ES9080 DAC, that I selected because it has an integrated output stage, preventing me to mess that part. It is an easy part.
I still look after a balanced design that avoids major mistakes ;-) Have to sleep on that
Sometime it is difficult for me to be synthetic. Sorry.
I have to do my homework about ground loops, that I understand are sort of sure thing if doing meadurements on the DAC performance with ADC without precautions.I still have to understand why there are not common issues when PC + DAC + Amplifier each has his power supply and no isolation between those? Or how are done the Audioscience review tests, where I don't see often discussed isolators?
One thing I appreciate in design, that I could word as "system engineering" is understanding the functions and allocating those to the correct subsystems to achieve good performance with "measured" means. Prefering simple solutions when possible... I started with the idea of versatile multichannel USB to I2S bridge, for Hobbyists interested in things like CamillaDSP to control active speakers (or speakers + subwoofers).
That bridge should possibly be a good companion for good to very good DACS, which I assimilated to (but not be sufficient):
- USB in asynchronous mode to have the clocks on the "controlled side" ( USB to I2S bridge)
- correct implementation of Audio frequencies oscillators for the 2 audio famillies,
- correct power management to minimize noise reaching the clock and the oscillators,
- possibly not so good: bridge as Master, generating MCLK and other I2S signals.
Not so simple...
As often, it can be more difficult to design a versatile component, able to cope with different intentions, than a dedicated one for an integrated design:
- having the MCLK on the DAC board looks better for performance, but would prevent the bridge to be able to control a SPDIF / Tolink daughter board,
- if the DAC is the Master, should it always generate WCLK and BCLK (I see several other variants in discussions above)?
- can the board that I'm designing (schematic earlier in the thread), with the stm32 SAI also work in slave mode? At which conditions?
- Isolators? Where?
And I know that this is purely intellectual, as the first target is a ES9080 DAC, that I selected because it has an integrated output stage, preventing me to mess that part. It is an easy part.
I still look after a balanced design that avoids major mistakes ;-) Have to sleep on that
Two questions:
I understand that, when working in slave mode, the stm32 SAI don't need the MCLK (I don't know for the XMOS chips).
Let's consider a USB to I2S bridge with I2S in Slave Mode and DAC with MCLK in I2S Master mode.
In that configuration, what are the benefits/use cases to import the MCLK from the DAC board back to the USB to I2S bridge?
I understand that, when working in slave mode, the stm32 SAI don't need the MCLK (I don't know for the XMOS chips).
Let's consider a USB to I2S bridge with I2S in Slave Mode and DAC with MCLK in I2S Master mode.
In that configuration, what are the benefits/use cases to import the MCLK from the DAC board back to the USB to I2S bridge?
Not all DACs support I2S master mode. E.g. AKM DACs only support slave mode (with the exception of AK4191+AK4499).
This was a Ahhhh moment... AKM only support Slave mode. Went back to datasheets, looked at the AK4493 evaluation board and the usage of the local NZ2520SD crystal...
I can't have things simple and make everything... So my bridge/controller current config can manage:
Let's consider that a configuration where the Bridge is is I2S Master, but uses an ext MCLK coming from the DAC is "exotic" and not for beginners.
I can't have things simple and make everything... So my bridge/controller current config can manage:
- I2S Master Bridge with local MCLK audio clock, DAC being Slave,
- I2S Slave Bridge, DAC being Master with its MCLK (MCLK not needed for bridge/controller),
Let's consider that a configuration where the Bridge is is I2S Master, but uses an ext MCLK coming from the DAC is "exotic" and not for beginners.
If a DAC can be only slave (like the AKM ones), and MCLK should be with the DAC - that would seem quite a common situation, IMO. Does the STM32 SAI support external MCLK input? It's common on linux ARM SoCs.
Because of a various ground loops, there will be high common mode signal at ADC input.
The insulation breaks this circuit if it has low capacitance (usually in the range of tens of pF).
A regular power transformer is also an isolated device, but the primary-secondary capacitance can reach several nF.
Another way - using differential (balanced) ADC input (even if DAC's output is not balanced). It helps a lot, but it's CMMR is not infinity, and decreases at high frequencies.
Professional Device with the starting (base) price ~$30K have a lot of features, including differential input. And are you sure that there is no isolation inside?
There have been many examples where, even with the AP555x or similar equipment, people have made incorrect measurements due to loops in the ground. It's good that Amir finally learned how to do this 🙂
Why?! It doesn't matter where the USB bridge gets the MCLK signal from. Or are you afraid of MCLC jitter in SPDIF? Don't worry, the SPDIF receiver will provide much higher jitter with its PLL, especially if it's an antique like the CS8412.
I'm not familiar with ES9080, but for ES9028/38 - in 90% cases used in async. mode, where it's own 90-100MHz clock used, wit PLL and ASRC. So these DAC can work w/o XXX*Fs MCLK. In this case not need to use MCLK oscillator close to the DAC.
the stm32 SAI don't need the MCLK (I don't know for the XMOS chips).
Yes, in slave mode SAI does not need MCLK.
XMOS also, but it depends of a library used.
Alex.
@altor: About the SPIF, my thinking was not very clear. The stm32 cans generate the SPDIF signals if we can generate the correct Audio frequences based on the HSE or MCLK input. So I need to consider in my design. If my design was "only slave", It couldd ne unable to generate the correct freq.
@phofman: Because I lack knowledege on high speed signals, I may consider risky some in fact easy things. And Vice Versa. I could consider a simple jumper at stm32 ext MCLK input to select either the signal forn the Audio crystals, or from the daughter boards MCLK (for bridge as Master, but with a DAC MCLK use case). Bit the buffer datasheet says to use 50R impedance lines toward the sinks. Is it OK tu put pin headers and jumpers there?
@phofman: Because I lack knowledege on high speed signals, I may consider risky some in fact easy things. And Vice Versa. I could consider a simple jumper at stm32 ext MCLK input to select either the signal forn the Audio crystals, or from the daughter boards MCLK (for bridge as Master, but with a DAC MCLK use case). Bit the buffer datasheet says to use 50R impedance lines toward the sinks. Is it OK tu put pin headers and jumpers there?
About SPDIF, when I asked what people would be intersted in, to my surprise, the few people that answered said that what they wanted was multi channel bridge to SPDIF, especially TOSlink.
This is not my need, but it's easy to have as a variant from USB to I2S through stm32/SAI. So why not offer the option.
JM
This is not my need, but it's easy to have as a variant from USB to I2S through stm32/SAI. So why not offer the option.
JM
For the SPDIF use case, 8 Channels where discussed, through 4 SPDIF ouputs. Those would be generated from 2x Stm32 SAI (A and B blocks). Each block can manage a stereo SPDIF => 2x2x2 = 8 channels. The SAI and blocks ca be synchronized on one of them being the "Master". The Master can be sync on on the I2SMCLK (external MCLK).
The stm32F743 has 4 SAI, so possibly more SAI and more SPDIF out, but the 100 pin package has some overlap, so only 12 or 14 channels would be achievable (don't remember exact limitation).
Devils being in details, I may have missed important things.
JMF
The stm32F743 has 4 SAI, so possibly more SAI and more SPDIF out, but the 100 pin package has some overlap, so only 12 or 14 channels would be achievable (don't remember exact limitation).
Devils being in details, I may have missed important things.
JMF