@MarkW dm pls for more info, links etc. Would love to expand and see more of that.
@MarcelVd could very well be, sadly it goes over my head what that really means, what the implications etc are. It is a quick software fix for a hardware problem and it does that excellently. The other settings have a bigger impact on SQ and I know of no other software/player that can do it.
What/how do you feed your discrete DACs?
@MarcelVd could very well be, sadly it goes over my head what that really means, what the implications etc are. It is a quick software fix for a hardware problem and it does that excellently. The other settings have a bigger impact on SQ and I know of no other software/player that can do it.
What/how do you feed your discrete DACs?
ISI, it is like "murmur" after the loud signal.
Of course, the test signals are made from PCM by software convertors (like Saracon) or in hardware (like AK4137).
But is it not so important because of a ISI.
Try this: https://albumplayer.ru/english.html
It is very good player (Win, Linux, R-Pi, etc.) and also can convert PCM>DSD, and it is free.
Alex.
Best PCM->DSD converter found so far (but its slow in high quality mode): https://pcmdsd.com/Software/PCM-DSD_Converter_en.html
It mainly means that the ultrasonic quantization noise indeed behaves similarly (though not identically) to additive noise. You don't get huge frequency-modulated tones near half the sample rate that can be mixed into the audio band by DAC imperfections, like you have with a plain single-bit sigma-delta modulator.
With an FPGA module and an SRC4392, see https://linearaudio.net/valve-dac-submicron-silicon-meets-submillimetre-vacuum-0 I always use it in the PWM9 mode.
You get a tone around half the sample rate that is FM modulated by the desired signal and the aliases of that modulated tone. The first alias is on the other side of half the sample rate, that is, quite close to the first tone when the desired signal is small. Pass it through something non-linear that produces a product at the frequency difference and it may end up in the audio band, especially at small levels of the desired signal.
Ted Smith (formerly of Microsoft; chief digital designer for PS Audio) began experimenting with DSD 12-13 years ago. He noted that he simply LPF'd the decoder from his Sony SACD player to get good results:
https://www.audioasylum.com/messages/pcaudio/80732/my-new-dac-long-but-with-pictures
https://www.audioasylum.com/messages/pcaudio/80732/my-new-dac-long-but-with-pictures
Short answer: yes.
More elaborate answer:
In a non-return-to-zero DAC (NRZ DAC) with unequal rise and fall times, a 1100 sequence gets a different average value than a 1010 sequence. That is, the weight of a bit depends in a non-linear way on the bits around it. Balancing can help, because every transition then means a low-to-high transition on one side and a high-to-low transition on the other side of the balanced output, compensating for the unequal transitions. Return-to-zero coding also helps, in fact it is quite effective.
Random clock jitter cannot mix idle tones to audio band tones, but spurious tones on the clock signal at or around half the sample rate (or some odd multiple of it) can. Examples: data signal with idle tones crosstalking onto the clock, use of a crystal oscillator at half the sample rate and a clock doubler that doesn't fully suppress its input frequency. I posted some simulations of the latter issue on Andrea Mori's low jitter thread, see posts 2830...2850 of https://www.diyaudio.com/community/...jitter-crystal-oscillator.261651/post-6372426
Interference on the DAC reference at or around half the sample rate or some odd multiple has pretty much the same effect, so crosstalk of the data signal to the reference has to be kept small for example, by making the current drawn from the reference as data-independent as possible. Spurs at exact integer multiples of the sample rate are harmless, so clock residues on the reference don't matter.
Over- and undershoots don't matter when, for example, each one has the exact same overshoot. It's a different issue as soon as there is a dependence on the previous bit.
You didn't mention a reconstruction filter with even-order distortion, but that can also do the trick.
A FIRDAC with a notch at half the sample rate suppresses idle tones before they can even reach the rest of the reconstruction filter, but it also reduces the sensitivity to clock disturbances around half the sample rate. With a FIRDAC, clock spurs phase modulate the FIRDAC output signal (because all branches are influenced equally when the clock transitions are early or late), and the idle tones are already suppressed to some extent in the FIRDAC output signal.
More elaborate answer:
In a non-return-to-zero DAC (NRZ DAC) with unequal rise and fall times, a 1100 sequence gets a different average value than a 1010 sequence. That is, the weight of a bit depends in a non-linear way on the bits around it. Balancing can help, because every transition then means a low-to-high transition on one side and a high-to-low transition on the other side of the balanced output, compensating for the unequal transitions. Return-to-zero coding also helps, in fact it is quite effective.
Random clock jitter cannot mix idle tones to audio band tones, but spurious tones on the clock signal at or around half the sample rate (or some odd multiple of it) can. Examples: data signal with idle tones crosstalking onto the clock, use of a crystal oscillator at half the sample rate and a clock doubler that doesn't fully suppress its input frequency. I posted some simulations of the latter issue on Andrea Mori's low jitter thread, see posts 2830...2850 of https://www.diyaudio.com/community/...jitter-crystal-oscillator.261651/post-6372426
Interference on the DAC reference at or around half the sample rate or some odd multiple has pretty much the same effect, so crosstalk of the data signal to the reference has to be kept small for example, by making the current drawn from the reference as data-independent as possible. Spurs at exact integer multiples of the sample rate are harmless, so clock residues on the reference don't matter.
Over- and undershoots don't matter when, for example, each one has the exact same overshoot. It's a different issue as soon as there is a dependence on the previous bit.
You didn't mention a reconstruction filter with even-order distortion, but that can also do the trick.
A FIRDAC with a notch at half the sample rate suppresses idle tones before they can even reach the rest of the reconstruction filter, but it also reduces the sensitivity to clock disturbances around half the sample rate. With a FIRDAC, clock spurs phase modulate the FIRDAC output signal (because all branches are influenced equally when the clock transitions are early or late), and the idle tones are already suppressed to some extent in the FIRDAC output signal.
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So the noise floor is around -135 dB in 0.4 Hz with respect to the maximum signal. A-weighting has a noise bandwidth of about 13 kHz (around 12.5 kHz when combined with a 20 kHz low-pass, about 13.5 kHz with no low-pass), so you have to add about 10 dB*log10(13000/0.4) ~= 45 dB to find the A-weighted noise level. That's about -90 dB(A). Pretty good for a single flip-flop!
Yes, they are!
By "balancing" you mean like with a differential transistor pair, right? Not in an adjacent parallel running discrete single ended cmos chip with it`s data inverted or anything, as this would cause weird common mode issues, also data dependent? I never got much better results out of it anyway, maybe my implementation was bad after all, or I`m too demanding, can`t say for sure ;-)
Clocks:
I would almost try a sine wave oscillator, or not fully squared ;-)
Never checked for interference, just followed good guidelines, did check with the tds820 (yeah, that old beast) for rise time, overshoot etc, no problems there, but haven't checked wit a scope when connected to the passive filter.
Given it was highly sensitive to clocks/clock signal coupling and amplitude, I suspected no real urgent issues there though.
Understood this far I think, will look into the second order reconstruction filter myself online before I bug you with more questions. Sofar the results on that topic seem a bit unclear, as I have absolutely no idea where to place the second order distortion part, but I`ll get back to that if I fail, if you don`t mind.
Thanks a lot for the insight Marcel. I learned more about this subject in the last 2 days than in the last 2 years.
Clocks:
I would almost try a sine wave oscillator, or not fully squared ;-)
Never checked for interference, just followed good guidelines, did check with the tds820 (yeah, that old beast) for rise time, overshoot etc, no problems there, but haven't checked wit a scope when connected to the passive filter.
Given it was highly sensitive to clocks/clock signal coupling and amplitude, I suspected no real urgent issues there though.
Understood this far I think, will look into the second order reconstruction filter myself online before I bug you with more questions. Sofar the results on that topic seem a bit unclear, as I have absolutely no idea where to place the second order distortion part, but I`ll get back to that if I fail, if you don`t mind.
Thanks a lot for the insight Marcel. I learned more about this subject in the last 2 days than in the last 2 years.
Maybe your single-ended circuit was already good enough 
I was thinking about two CMOS flip-flops with inverted data, followed by a circuit that looks at the differential signal and suppresses common-mode disturbances. A single flip-flop that is symmetrical by design and that has a Q and a Qnot is also possible, but most CMOS flip-flops are not symmetrical; maybe ECL flip-flops are.
I was thinking about two CMOS flip-flops with inverted data, followed by a circuit that looks at the differential signal and suppresses common-mode disturbances. A single flip-flop that is symmetrical by design and that has a Q and a Qnot is also possible, but most CMOS flip-flops are not symmetrical; maybe ECL flip-flops are.
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With 150 watts amps directly behind that and medium efficient speakers connected, there could be audible noise when close in front of it and a wrong termination, connection etc. occurred. If well configured that was gone and the analyzer showed good, but not extreme improvement, so I figured it was around that just acceptable value more or less. Enjoyable result without any artifacts, yes it was, thanks.
So without A-weighting it`s: noise floor - 10 dB*log10 (bandwith/X)? X = Fs/N, N = FFT points, Fs is Sample Rate of the ADC, awesome I get it.
Normal weighing is in that case (48 Khz ADC): 135- 47 = 88 dB. Always wondered this.
Your last message displays I didn`t explain well: yes my implementation with the differential logic was better, but my experiments with 2 cmos, 1 of them inverted data version of the other wasn`t a great succes.
All ECL FF`s are symmetrical by design, but sure you could use a single ended output, but you might need to terminate the unused output, depending how you "wired them up" ;-)
So without A-weighting it`s: noise floor - 10 dB*log10 (bandwith/X)? X = Fs/N, N = FFT points, Fs is Sample Rate of the ADC, awesome I get it.
Normal weighing is in that case (48 Khz ADC): 135- 47 = 88 dB. Always wondered this.
Your last message displays I didn`t explain well: yes my implementation with the differential logic was better, but my experiments with 2 cmos, 1 of them inverted data version of the other wasn`t a great succes.
All ECL FF`s are symmetrical by design, but sure you could use a single ended output, but you might need to terminate the unused output, depending how you "wired them up" ;-)
For the record, I tried Andrea's clocks with doublers and without them to produce 22/24MHz clocks for use with my AK4499 dac (11/12MHz then doubled, or else 22/24MHz non-doubled). I was expecting possible trouble with the doublers. However, version with doublers sounded overall a little bit better. Could be AK4499 has some degree of immunity to whatever clock aberrations may have been present. Don't know. Do know overall measured close-in phase noise of the clocks was less with doublers.
I wouldn't be surprised if the clock would internally be divided again in the AK4499. Browsing through the datasheet, I haven't found the actual sigma-delta modulator sample rate, but I did see on page 45 that the AK4499 can work with half or 3/4 of the clock rate you use. Chances are that it divides the clock you apply by four, eliminating the subharmonics.
https://media.digikey.com/pdf/Data Sheets/AKM Semiconductor Inc. PDFs/AK4499_Feb2019.pdf
https://media.digikey.com/pdf/Data Sheets/AKM Semiconductor Inc. PDFs/AK4499_Feb2019.pdf