I found some toroidal through hole 7.5VAC transformers with 500MA per secondary here if the others are harder to source. Green Cube SEALED Transformer 7 5V 7 5V SN | eBay
Not my auction, I just bought one.
Not my auction, I just bought one.
Like I said, I have not done a comparison of I2S vs. s/pdif with a FIFO buffer. I know that the FIFO is supposed to "pick up the slack" in both cases (jitter-wise), but the audio-phool in me keeps telling me to doubt its effectiveness, when it comes to s/pdif.
I guess I'll just have to try them both to convince myself.
I really shouldn't have these doubts. I'm after all a computer engineer. But I guess I've hanged around with audiophiles for too long.
Dimdim - Its obvious that you dont know how a fifo works, or...
if you did - you would know that the received data (1's and 0's) is written in to a memory. After a while, it's read out and passed down to the actual D/A peocess. How on earth could the data after it has been stored in a memory *for* *a* *while* have any whatsoever trace of any jitter (ideal arrival in time for a piece of information or clock) it had before the memory?
We must have some logic law & order here
//
if you did - you would know that the received data (1's and 0's) is written in to a memory. After a while, it's read out and passed down to the actual D/A peocess. How on earth could the data after it has been stored in a memory *for* *a* *while* have any whatsoever trace of any jitter (ideal arrival in time for a piece of information or clock) it had before the memory?
We must have some logic law & order here
//
I surmise DIMDIM like me is involved by computer enginneering and the proves of concepts we often need to be sure... working sometimes in wild environment with too much parametrizes & nestings ?!
Yes I know it seems illogical, but not too much for me, in the computers world many of us suffer of the paradigm crisis: : all is good till the next proof then next paradigm ! profesional deformation
Yes I know it seems illogical, but not too much for me, in the computers world many of us suffer of the paradigm crisis: : all is good till the next proof then next paradigm ! profesional deformation
Dimdim - Its obvious that you dont know how a fifo works, or...
if you did - you would know that the received data (1's and 0's) is written in to a memory. After a while, it's read out and passed down to the actual D/A peocess. How on earth could the data after it has been stored in a memory *for* *a* *while* have any whatsoever trace of any jitter (ideal arrival in time for a piece of information or clock) it had before the memory?
We must have some logic law & order here
//
The PLL that controls the XO and therefore the FIFO is a low pass filter with a corner frequency of 0.01Hz. This means the amplitude of jitter will be reduced by half at 0.01Hz and decrease further as the frequency increases depending on the slope of the filter.
So there is potential for low frequency jitter to bypass the FIFO. It is a good reason to galvanically isolate your inputs.
cheers
Paul
You need to add the 0.1uF between Vcc and GND close to the pins - or within 7mm.
It might be worth adding the 47uH inductor in the power supply line as suggested by the data sheet.
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Dimdim - Its obvious that you dont know how a fifo works, or...
if you did - you would know that the received data (1's and 0's) is written in to a memory. After a while, it's read out and passed down to the actual D/A peocess. How on earth could the data after it has been stored in a memory *for* *a* *while* have any whatsoever trace of any jitter (ideal arrival in time for a piece of information or clock) it had before the memory?
We must have some logic law & order here
//
I myself are a big fan of logic, law & order, but this is audio, so as we have seen many times in the past, what appears to be "logical" turns out to be.. well.. not so "logical".
For example the de-jittering function of the ES9018. It was supposed to be perfect. We all know how that went..
So, since I do not know (in detail) the inner workings of Soren's FPGA, I prefer to err in the side of caution.
The FIFO does indeed sort out the timing of the bit streams, that much is a given. But subtle details about its operation also matter too. For example, one could say that Ian's FIFO does the same thing, but it doesn't. At least, not exactly.
As was stated a few post back, low frequency jitter could pass through the FIFO.
If the FIFO was a total solution, we should not be picky about choosing pulse transformers, for example.. just get the cheepest one you can find.
Aside from all that, I trully hope that this specific FIFO is indeed an excellent implementation that does indeed level the playing field regarding the various inputs.
I have SPDIF and TOSLINK running. There are differences between the two in terms of SQ, the TOSLINK sounds very slightly more full bodied but also slightly less focused. The space around instruments and vocals is slightly less clearly defined for example. They sound close but not the same.
I'm going to try placing a 47uH inductor on the TOSLINK power line as per the datasheet.
It's worth keeping in mind that there may be mechanisms at work that aren't obvious. John Swenson has posted about measurable levels of power noise passing through isolators into DAC circuits for example, (see Mac Mini version of a CAPS music server - Step by Step - Page 9 ).
cheers
Paul
Regarding the coax vs. toslink case, your conclusions agree with my findings from other DACs that I have built in the past. However, I have not done a comparison on the Soekris. I'm still waiting delivery of my TORX147s.
Viva la Prove of Concept....
there is often a parameter we forget to manage ! The experiment is here to predict (to test) or not what the theory says. The more we know, the more the experiment will glue to it, but there is sometimes something we forget (or don't know or missunderstood, or a non predicted interaction)... so Viva la POC !
Is there any european and member from the pacific side to link (for the first page) here a cheap USB to serie adaptor for laptops (included: W 64 bits) ?
there is often a parameter we forget to manage ! The experiment is here to predict (to test) or not what the theory says. The more we know, the more the experiment will glue to it, but there is sometimes something we forget (or don't know or missunderstood, or a non predicted interaction)... so Viva la POC !
Is there any european and member from the pacific side to link (for the first page) here a cheap USB to serie adaptor for laptops (included: W 64 bits) ?
I use this one which works fine with a Mac. From OS 10.9 on the driver for the used FTDI chip come with the system, for earlier versions and other operating systems you find them on the FTDI home page.
Digitus USB auf Seriell DB9 Adapter schwarz: Amazon.de: Computer & Zubehör
Did you have any change to compare between them with I2S, Paul? And please let us known your opinion after adding 47uH...
Thanks.
So any testimonies about AC vs DC for power supplying the DAM1201.
I tried the buffered SE without too much difference with the non buffered SE ! a slight difference in mid-bass, but not decisiv !
Urgent to load a [FONT=geneva,arial] [/FONT]ISO X ( ISO 2969) curve for have a better point of view to know its real possibilities ?
Is it easy and fast for Soren to copy such a curve for a soft revision ? I have no idea of the time involved for such work ?
I tried the buffered SE without too much difference with the non buffered SE ! a slight difference in mid-bass, but not decisiv !
Urgent to load a [FONT=geneva,arial] [/FONT]ISO X ( ISO 2969) curve for have a better point of view to know its real possibilities ?
Is it easy and fast for Soren to copy such a curve for a soft revision ? I have no idea of the time involved for such work ?
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