Folks,
Over in the other meta thread we have been discussing the TDA1541.
https://www.diyaudio.com/community/threads/building-the-ultimate-nos-dac-using-tda1541a.79452/
Based on my experiences, various articles and application notes and practical work by a number of peeps we now have a pretty decent understanding of the TDA1541 and what makes it really tick. Much of it is in line with my previous understanding, but where before I had many black boxes I now have a better feel for the internal circuits and the various implications.
In short:
1) The TDA1541 needs a syncronised DEM system with correctly sized DEM filter capacitors and a way of feeding the DEM Oscillator pin's that do not cause DEM switching feed trough into the substrate. Empirically 8 X DEM Clocks (352.6/384kHz) offer the best objective performance.
Very low frequency DEM oscillators with big value electrolytic capacitors are an alternative but a bit questionable insofar as it takes hours of the DAC running to get to correct operation and long term stability is highly questionable. In the end both achieve the same fundamental result in different ways.
2) The TDA1541 has significant capacitive feedthrough from the digital inputs into the substrate and from there into the outputs. It is best imagined as a coupling capacitor of ~ 12pF between each digital input and the analogue outputs. 12pF does not sound like much but with MHz bit clock frequencies there is a lot of feedthrough.
Slowing down the edges of the input signals will reduce this. By using "Simultaneous Mode" we can lower the Bit Clock frequency maximally. At 192kHz Sample Rate we only have 3.072MHz Bit clock in this case. It means the edges can be slowed down much more without ill effects on the digital side, compared to I2S mode which typically has 12.288MHz Bit clock at 192kHz.
Existing "SIM" converters unfortunately (almost) all use the fallacious "stopped clock" system, which maximises the clock speed so a lot of clock feedthrough happens for a short duration and then nothing for the rest. This means we cannot slow down BCK edges too much, nor any others. So I will not consider such systems desirable.
There are debates around analogue stages and other TDA1541 related circuitry, but they are not (yet?) part of this project.
So, what is the project?
Make a PCB design (open sauce, free as in Free Speech and Free Beer) for a TDA1541(A) frontend that accepts an Amanero standard USB Module, incorporates an SPDIF receiver (optical, Coax and XLR) and includes an IIS to Simultaneous converter that outputs a continuous BCK at 16 X FS and the necessary LE Signal and Data and slew rate and voltage swing limiter circuitry.
Just add a TDA1541 (we might bring the IC position onto the PCB with other bits, this remains to be seen), power and analogue stage (where nobody seems to agree on anything).
As this is DIY Audio, we want to do this in discrete logic, not using CPLD or FPGA or bought in CPLD/FPGA Modules. Why no complex logic? Typically we find a few 100pS P-P additive Jitter from CPLD, FPGA or CPU's (e.g. XMOS). Ground bounce and other problems are significant. The IC cases are distinctly DIY unfriendly, a tool chain and programmer is also needed. It adds up. We can reclock to block a lot of this, but still, why?
With an Amanero Footprint (we can add more) the USB input is taken care of. For SPDIF the WM8804/05 series is EOL and others re unclear. So adding a CS8412(14) footprint is probably easiest, we can add suitable adapter PCB's for WM8804, CS8416/DP7416, AK4118 etc. on the PCB.
The main challenge is that we need to take a BCK of 64 X FS and a 2 X 32 Bit Data steam on one data line and output a BCK that is divided by 4 and two Data lines that have 16 Bit Per sample.
There are a number of possible approaches using shift registers, but as we need an input register to hold data from the I2S input (say 8 X 74HC595) and then an output register (say 4 X 74HC165) to hold 16 Bit that go to the TDA1541, this rapidly becomes a logic IC grave. We can find some 16 Bit Shift registers but these still account for a lot of circuitry.
On the plus side, the logic in this case becomes very transparent, obvious and easy to design and debug. Still 16 IC's or so seem a lot to me. It does remain an option.
An alternative would be to use the 74HC(T)40105 FIFO. As we have separate input and output clocks and the "elastic" FIFI we can stuff our 16 Bit into the Input side at the 64 X BCK speed and clock our data out steadily at 16 X BCK and the FIFO takes care of everything.
This would use one 40105 FIFO configured as 64 Bit Delay line with data taps at 16/32/48 and 64 Bit's so we can have the input bit's for our FIFO arrive simultaneously.
Two more 40105 FIFO handle data build as a 32 Bit X 4 FIFO. We stuff bit's into the first FIFO from where the ripple immediately to the output. We then clock out using our 16 X FS BCK. On the input side we invert MSB and only pass actual 16 Data bits, stopped input clock to block off the rest.
I think the FIFO solution is by far more elegant. An option for a secondary PLL with VCXO (or a VCLCXO) can be designed in as well.
A discussion start is here:
https://www.diyaudio.com/community/...ac-using-tda1541a.79452/page-517#post-7939329
So, if anyone wants to join into the discussion and project, feel free.
Thor
Over in the other meta thread we have been discussing the TDA1541.
https://www.diyaudio.com/community/threads/building-the-ultimate-nos-dac-using-tda1541a.79452/
Based on my experiences, various articles and application notes and practical work by a number of peeps we now have a pretty decent understanding of the TDA1541 and what makes it really tick. Much of it is in line with my previous understanding, but where before I had many black boxes I now have a better feel for the internal circuits and the various implications.
In short:
1) The TDA1541 needs a syncronised DEM system with correctly sized DEM filter capacitors and a way of feeding the DEM Oscillator pin's that do not cause DEM switching feed trough into the substrate. Empirically 8 X DEM Clocks (352.6/384kHz) offer the best objective performance.
Very low frequency DEM oscillators with big value electrolytic capacitors are an alternative but a bit questionable insofar as it takes hours of the DAC running to get to correct operation and long term stability is highly questionable. In the end both achieve the same fundamental result in different ways.
2) The TDA1541 has significant capacitive feedthrough from the digital inputs into the substrate and from there into the outputs. It is best imagined as a coupling capacitor of ~ 12pF between each digital input and the analogue outputs. 12pF does not sound like much but with MHz bit clock frequencies there is a lot of feedthrough.
Slowing down the edges of the input signals will reduce this. By using "Simultaneous Mode" we can lower the Bit Clock frequency maximally. At 192kHz Sample Rate we only have 3.072MHz Bit clock in this case. It means the edges can be slowed down much more without ill effects on the digital side, compared to I2S mode which typically has 12.288MHz Bit clock at 192kHz.
Existing "SIM" converters unfortunately (almost) all use the fallacious "stopped clock" system, which maximises the clock speed so a lot of clock feedthrough happens for a short duration and then nothing for the rest. This means we cannot slow down BCK edges too much, nor any others. So I will not consider such systems desirable.
There are debates around analogue stages and other TDA1541 related circuitry, but they are not (yet?) part of this project.
So, what is the project?
Make a PCB design (open sauce, free as in Free Speech and Free Beer) for a TDA1541(A) frontend that accepts an Amanero standard USB Module, incorporates an SPDIF receiver (optical, Coax and XLR) and includes an IIS to Simultaneous converter that outputs a continuous BCK at 16 X FS and the necessary LE Signal and Data and slew rate and voltage swing limiter circuitry.
Just add a TDA1541 (we might bring the IC position onto the PCB with other bits, this remains to be seen), power and analogue stage (where nobody seems to agree on anything).
As this is DIY Audio, we want to do this in discrete logic, not using CPLD or FPGA or bought in CPLD/FPGA Modules. Why no complex logic? Typically we find a few 100pS P-P additive Jitter from CPLD, FPGA or CPU's (e.g. XMOS). Ground bounce and other problems are significant. The IC cases are distinctly DIY unfriendly, a tool chain and programmer is also needed. It adds up. We can reclock to block a lot of this, but still, why?
With an Amanero Footprint (we can add more) the USB input is taken care of. For SPDIF the WM8804/05 series is EOL and others re unclear. So adding a CS8412(14) footprint is probably easiest, we can add suitable adapter PCB's for WM8804, CS8416/DP7416, AK4118 etc. on the PCB.
The main challenge is that we need to take a BCK of 64 X FS and a 2 X 32 Bit Data steam on one data line and output a BCK that is divided by 4 and two Data lines that have 16 Bit Per sample.
There are a number of possible approaches using shift registers, but as we need an input register to hold data from the I2S input (say 8 X 74HC595) and then an output register (say 4 X 74HC165) to hold 16 Bit that go to the TDA1541, this rapidly becomes a logic IC grave. We can find some 16 Bit Shift registers but these still account for a lot of circuitry.
On the plus side, the logic in this case becomes very transparent, obvious and easy to design and debug. Still 16 IC's or so seem a lot to me. It does remain an option.
An alternative would be to use the 74HC(T)40105 FIFO. As we have separate input and output clocks and the "elastic" FIFI we can stuff our 16 Bit into the Input side at the 64 X BCK speed and clock our data out steadily at 16 X BCK and the FIFO takes care of everything.
This would use one 40105 FIFO configured as 64 Bit Delay line with data taps at 16/32/48 and 64 Bit's so we can have the input bit's for our FIFO arrive simultaneously.
Two more 40105 FIFO handle data build as a 32 Bit X 4 FIFO. We stuff bit's into the first FIFO from where the ripple immediately to the output. We then clock out using our 16 X FS BCK. On the input side we invert MSB and only pass actual 16 Data bits, stopped input clock to block off the rest.
I think the FIFO solution is by far more elegant. An option for a secondary PLL with VCXO (or a VCLCXO) can be designed in as well.
A discussion start is here:
https://www.diyaudio.com/community/...ac-using-tda1541a.79452/page-517#post-7939329
So, if anyone wants to join into the discussion and project, feel free.
Thor
Ok,
Here previous discussion:
Before I expressed my dissatisfaction with the IIS2SIM converters that use stopped clock and commented that I was not fond of CPLD/FPGA solutions.
I happen to feel that driving the Digital Inputs with lowest frequencies possible, with slew rate limited edges causes the least digital noise breakthrough into the output.
So to me the "ideal" IIS2SIM converter (TDA1541 specific) takes in IIS at BCK = 64 X FS and generates a BCK with 16 X FS, a narrow LE pulse and two 16 Bit Data streams with MSB inverted.
The raptorlightnighting FPGA in principle does that, has source code available and all that. Nice. But I still prefer something with more discrete logic.
I was looking at the jitter killer system in the Marantz DA-12 / Marantz PM-75 / Philips LHH-1000.
It's a quite involved way to make a 16 Bit FIFO:
A pair of 16 Bit shift registers is used to create a series to parallel conversion, then parallel to serial and clock out via "slow PLL Clock".
I remembered before using the 74HC40105 FIFO in a circuit to delay IIS data to allow 3-wire EIAJ to 4-wire EIAJ format conversion.
We can use stopped clock to bang the right serial bit's into the pipeline and then use our original BCK divided by 4 to clock out our data. We need one IC per Channel and would only use one of the 4 Lanes.
I checked availability and it remains at Mouser from TI. Only. ~ 3,700 in stock, 12 weeks leadtime. HC & HCT versions. Under 1 USD.
It would be neat to build an IIS2SIM converter using 74HC(T)40105, but I expect NRND or EOL some time soon. I could not find any second source with production. Shame that.
The 74ACT2226 would be even better. Two completely separate 64 Bit FIFO's. But nobody I can find stocks it. Direct order from TI only.
With 64 Bit we can "assemble" two full 16 Bit words before we clock out the first word and have always +/- 1 word margin. Two independent FIFO's mean we just need this IC. On the input we select which FIFO receives BCK based on FSYNC/WCK +
With the goal of only ever driving TDA1541, nothing else and integrating everything on Board. Attenuators, DEEM reclocking. I'd even throw on a CS8416 (aka DP7416 - Chinese copy in TSSOP) on board, multiplexing to an Amanero footprint. Add a basic TDA1541 Board (even vero board) or onboard it, for the core of a "Killa DAC".
We would divide BCK by 4 with low jitter parts (74S74?) and use that to clock the FIFO and a final set of 74S74 Latches with flying attenuators to drive TDA1541.
Logic on the input side would need a "clock stopper" that masks off unwanted bits, an XOR that allows MSB Inversion on either input or output. Need to think on that one.
Is anyone interested in a "discrete logic" IIS2SIM design using 70HC(T)40105 or 74ACT2226 despite the caveats, the sketchy ideas and all that anyway?
Instead of the raptorlightning FPGA. I have been unable to get hold of him.
So for our problem of having on the input side 64 clock cycles but only 16 bit's of data out of 64 actual Bits possible and on the output side and 16 clock cycles, a FIFO is an ideal construct.
We bang our 16 bit's from our IIS source into the pipeline by stopping the input clock when we have "unwanted" bits.
Now our 16 bit wanted data is in the pipeline. On the output we steadily clock out these 16 Bit at a much lower clock rate.
The FIFO absorbs the differences in clock speed. As long as we always have 16 bit into the pipeline in the time we take 16 bit's out, the FIFO fill level grows and contracts depending on incoming data.
But as long as there is at least 1 bit left in the pipeline to clock out, the data out flows, to use a cheap pun like clock work...
The hc7403 looks interesting, but it seems essentially unavailable from any substantial source.
The hc40105 remain in long supply at 60 cent each. It can be cascaded to 32 bit.
I think a logic can be made that passes LE + DATAL + DATAR through a 32 Bit FIFO.
If we use a third FIFO, we can make it a 64 bit delay (that's how I used it) so we get L/R data simultaneously with one sample delay.
Yes, 3 pcs 40105. But little else is then needed.
The hc7403 FIFO or the hc2226 FIFO's make for a more elegant design.
Thor
Here previous discussion:
Before I expressed my dissatisfaction with the IIS2SIM converters that use stopped clock and commented that I was not fond of CPLD/FPGA solutions.
I happen to feel that driving the Digital Inputs with lowest frequencies possible, with slew rate limited edges causes the least digital noise breakthrough into the output.
So to me the "ideal" IIS2SIM converter (TDA1541 specific) takes in IIS at BCK = 64 X FS and generates a BCK with 16 X FS, a narrow LE pulse and two 16 Bit Data streams with MSB inverted.
The raptorlightnighting FPGA in principle does that, has source code available and all that. Nice. But I still prefer something with more discrete logic.
I was looking at the jitter killer system in the Marantz DA-12 / Marantz PM-75 / Philips LHH-1000.
It's a quite involved way to make a 16 Bit FIFO:
A pair of 16 Bit shift registers is used to create a series to parallel conversion, then parallel to serial and clock out via "slow PLL Clock".
I remembered before using the 74HC40105 FIFO in a circuit to delay IIS data to allow 3-wire EIAJ to 4-wire EIAJ format conversion.
We can use stopped clock to bang the right serial bit's into the pipeline and then use our original BCK divided by 4 to clock out our data. We need one IC per Channel and would only use one of the 4 Lanes.
I checked availability and it remains at Mouser from TI. Only. ~ 3,700 in stock, 12 weeks leadtime. HC & HCT versions. Under 1 USD.
It would be neat to build an IIS2SIM converter using 74HC(T)40105, but I expect NRND or EOL some time soon. I could not find any second source with production. Shame that.
The 74ACT2226 would be even better. Two completely separate 64 Bit FIFO's. But nobody I can find stocks it. Direct order from TI only.
With 64 Bit we can "assemble" two full 16 Bit words before we clock out the first word and have always +/- 1 word margin. Two independent FIFO's mean we just need this IC. On the input we select which FIFO receives BCK based on FSYNC/WCK +
With the goal of only ever driving TDA1541, nothing else and integrating everything on Board. Attenuators, DEEM reclocking. I'd even throw on a CS8416 (aka DP7416 - Chinese copy in TSSOP) on board, multiplexing to an Amanero footprint. Add a basic TDA1541 Board (even vero board) or onboard it, for the core of a "Killa DAC".
We would divide BCK by 4 with low jitter parts (74S74?) and use that to clock the FIFO and a final set of 74S74 Latches with flying attenuators to drive TDA1541.
Logic on the input side would need a "clock stopper" that masks off unwanted bits, an XOR that allows MSB Inversion on either input or output. Need to think on that one.
Is anyone interested in a "discrete logic" IIS2SIM design using 70HC(T)40105 or 74ACT2226 despite the caveats, the sketchy ideas and all that anyway?
Instead of the raptorlightning FPGA. I have been unable to get hold of him.
So for our problem of having on the input side 64 clock cycles but only 16 bit's of data out of 64 actual Bits possible and on the output side and 16 clock cycles, a FIFO is an ideal construct.
We bang our 16 bit's from our IIS source into the pipeline by stopping the input clock when we have "unwanted" bits.
Now our 16 bit wanted data is in the pipeline. On the output we steadily clock out these 16 Bit at a much lower clock rate.
The FIFO absorbs the differences in clock speed. As long as we always have 16 bit into the pipeline in the time we take 16 bit's out, the FIFO fill level grows and contracts depending on incoming data.
But as long as there is at least 1 bit left in the pipeline to clock out, the data out flows, to use a cheap pun like clock work...
The hc7403 looks interesting, but it seems essentially unavailable from any substantial source.
The hc40105 remain in long supply at 60 cent each. It can be cascaded to 32 bit.
I think a logic can be made that passes LE + DATAL + DATAR through a 32 Bit FIFO.
If we use a third FIFO, we can make it a 64 bit delay (that's how I used it) so we get L/R data simultaneously with one sample delay.
Yes, 3 pcs 40105. But little else is then needed.
The hc7403 FIFO or the hc2226 FIFO's make for a more elegant design.
Thor
Great idea! I would be interested to see a version that can take in the output of a DF (like DF1706 or PMD200) and generate buffered output with stopped clock for the TDA in simultaneous mode or for other DAC chips, all modular.
Suggestion was LC89091 over mediocre CS8412/14/16 but it is also obsolete now I noticed.
Only acceptable one left in the arena seems to be AK4118.
Only acceptable one left in the arena seems to be AK4118.
AK4118 is a fine choice, i would go for after wm8804. But there will be enough wm8804 for a while from unofficial stocked up people/shops, it went obsolete just last year. But socket is there in any case, so there will be several options designed just to swap in.
On the topic itself, i cannot help with this, my knowledge in digital is not extensive. Hope someone can pitch in, it is a nice idea.
On the topic itself, i cannot help with this, my knowledge in digital is not extensive. Hope someone can pitch in, it is a nice idea.
First, "stopped clock" is counter productive for TDA1541. It is much easier to do, but not the point here.
Second, most of modern DF's are 8X oversampling, that's seriously pushing it.
So you will have to do that yourself.
Thor
The 8416 is not that bad, BUT there are caveats. First, preamble locking must be used. This leaves fairly large levels of random noise jitter. Second, the PLL must be optimised
The random noise jitter is low enough for 16 Bit.
I tested AK4113, it was much worse than CS8416. WM880x is significantly superior.
But I don't want a long debate on which SPDIF receiver to use use. Hence put on a CS8412 footprint and buy whichever receiver you want from.Ali, they all come on CS8412 adapters.
Thor
I did already something myself, please see here. I need only to add MSB inverter and stopped clock to make it compatible with PMD200. Is 8x speed such a big problem?
Stopped clock helps not only for TDA: I thought you wanted your project also to work with other DAC chips. What is bad about stopped clock with TDA in your opinion?
4113 is different from 4118: 4118 is one of the best solutions. WM is obsolete. The choice of spdif is easy: use the best that is available = 4118.
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Do you understand what the problem with the TDA1541 is? Actually, there are really three distinct ones?
One problem is that the input transistors are PNP on a process that makes almost exclusively NPN.
As a result they have extremely high capacitance from base to substrate. The substrate is 10's of Ohm to -15V.
The 16 Output switches have their collectors made in a similar way as input transistors make their base.
So each input has ~ 12pF to substrate and then 16 X 12pF to the output.
So any edges on the input ride straight through to the output and to other bits of circuitry.
So, the faster the clock speed, the faster the edges need to be to allow the TDA1541 to correctly work. The crappy planar PNP inputs mean that higher frequencies actually need relatively faster edges to reliably trigger the inputs.
To minimise this behavior the best solution is to slew rate limit the edges going into the digital inputs. The slower the slew rate, the less unwanted digital noise is coupled into the IC.
Now, as corollary, the slower the clocks into the TDA1541, the slower the edges can be.
Thus, all else being equal, the TDA1541 is best operated at sample rates of <= 192kHz (even if faster is possible performance degrades), with a syncronised DEM frequency of 352.6/384khz and with the slowest clock speeds possible (which needs simultanious mode).
If you want massive oversampling ratios, ESS delivers that.
Anyway, I am only interested in optimising the TDA1541 for non-oversampling operation, without digital filter.
Stopped clock DOES NOT help TDA1541, it creates problems by forcing the use of a high clock frequency. The TDA1541 is not a CMOS IC, but ECL and current steering. So there no ground bounce and there is no "conversion" etc.
I explicitly stated I wanted TDA1541 ONLY ONLY ONLY.
There is universal stuff out there, with stopped clock etc.
There would be no point to develop anything new if that is what I wanted.
It forces faster clocks that necessary and thus causes extra digital switching noise to enter the IC.
Based on what others measured, it is not:
To wrap-up my monologue here are some jitter measurements.
1. SPDIF (Coax) - AK4118 - AK4490
There are strange artifacts about 85Hz apart. These are the same artifacts as shown in previous post. I assume these are somehow related to AK4118 PLL.
Now let's add AK4137 into the stream.
2. SPDIF (Coax) - AK4118 - AK4137 - AK4490
This looks much better. The reclocking done by AK4137 seems to remove most...
1. SPDIF (Coax) - AK4118 - AK4490
There are strange artifacts about 85Hz apart. These are the same artifacts as shown in previous post. I assume these are somehow related to AK4118 PLL.
Now let's add AK4137 into the stream.
2. SPDIF (Coax) - AK4118 - AK4137 - AK4490
This looks much better. The reclocking done by AK4137 seems to remove most...
That is pretty poor. CS8416 in preamble lock mode is much cleaner if higher random noise floor.
Now we can debate if correlated or random jitter sounds worse, but I am not interested.
Outside the datasheet and urban legends the AK4118 is the worst currently available solution. Which is why I do not want to use it.
Sadly Cirrus EOL'ed it. And did not yet propose a replacement.
I already came across a Taiwan made part that claimed to be a replacement for 8804/05 with the same DPLL system, however, it was not pin compatible and there was no EVM, so I left it alone.
A mainland fab now makes the DP7416 which is a function and pincompatible (like die identical) second option for CS8416.
Maybe they will get around to cloning the 8804/05. While I disapprove of Clones, I think once IC's are EOL'ed by the OEM, they are fair game for cloning.
Suit yourself. If I want the best reliably available long term with 16-Bit equivalent Jitter performance from high jitter sources I know which part to choose and it is not that one.
You seem to adhere to many folk tales that have little basis in reality. Please use the AK4118. We need to keep AKM in business. I'm not interested in this discussion. Thank you.
Thor
Maybe it was meant that this IC is still available and you mentioned the IC yourself too in the first post. All the others seem to be obsolete. Designing with obsolete stuff is a habit but for builders possibly a challenge. And when using Aliexpress modules in CS8412 format, one never knows what parts are used.
WM8804/5 are fine, these should still be around at distributors. If TDA1541(A) can be found after decades WM8804/5 should not be a problem 🙂 Digikey has 592 of them for now 12 Euro/piece (crazy, these used to be 4 Euro):
https://www.digikey.de/de/products/detail/cirrus-logic-inc/WM8804GEDS-V/5409936
WM8804/5 are fine, these should still be around at distributors. If TDA1541(A) can be found after decades WM8804/5 should not be a problem 🙂 Digikey has 592 of them for now 12 Euro/piece (crazy, these used to be 4 Euro):
https://www.digikey.de/de/products/detail/cirrus-logic-inc/WM8804GEDS-V/5409936
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All devices using AK4118 (without AK4137) show similar jtest results. Some worse, some better.
https://www.audiosciencereview.com/...toslink-optical-audio-measurements-png.55222/
https://www.audiosciencereview.com/...-dac-xlr-jitter-audio-measurements-png.43481/
I haven't seen any similar jitter measurements with WM8804/05 or CS8412/14/16 so difficult to say how much better those are compared to AK4118.
https://www.audiosciencereview.com/...toslink-optical-audio-measurements-png.55222/
https://www.audiosciencereview.com/...-dac-xlr-jitter-audio-measurements-png.43481/
I haven't seen any similar jitter measurements with WM8804/05 or CS8412/14/16 so difficult to say how much better those are compared to AK4118.
Thanks for clarifying. I get the point about stopped clock needing higher freq, but the stopping itself can help to update the output during a relatively quiet moment - at least with other DAC chips. The thread title says "and or universal multibit" and I think making such a nice project only for the TDA would be a pity if not a waste. Also I am not interested in NOS for obvious reasons.
Regarding your claim about 192k being the best speed for the TDA: did you listen to 4x vs 8x with the TDA? How would you describe the difference in sound quality?
Regarding your claim about 192k being the best speed for the TDA: did you listen to 4x vs 8x with the TDA? How would you describe the difference in sound quality?
Bohrok, Sanskrit 10 Mk II (and possibly Mk III too) used LC89091 AFAIK. Modded these and noticed them more than once. Also EOL.
I think I’ll buy those 592 WM8804 from Digikey 😉 Never had any complaint about the WM8804 contrary to CS8412 etc. or the absolute horror YM3623B.
I think I’ll buy those 592 WM8804 from Digikey 😉 Never had any complaint about the WM8804 contrary to CS8412 etc. or the absolute horror YM3623B.
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Possibly after AKM fire but also AK4118. SMSL (and other Chinese DAC makers) has the tendency to sand off chip markings.
But just to make my case regarding AK4118 jitter measurements here is Topping E30II:
https://www.audiosciencereview.com/...r-toslink-coax-measurement-stereo-png.220682/
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Yes, which is I would add actual adapter PCB's for breakoff and populating.
I do not want to "bake" them into the PCB without alternative options for the day they are 100 USD, like TDA1541, which used to be a few Bux...
https://www.audiosciencereview.com/...-s-pdif-digital-audio-filter.2189/#post-59399
This product "reviewed" is based on a WM880X with additional circuitry
Measurements I did are here:
https://audiophilestyle.com/forums/topic/28851-new-launch-spdif-ipurifier/page/3/
We fed different DAC's this:
Here is what we got:
Note that CS8416 was set to "fast mode". In "slow mode" it actually kills jitter quite well. But the noisefloor is up.
Objectively, when properly optimised (layout, power supplies and crystal) I measured on average between 10-20pS RMS jitter on MCK and in the analogue output.
It is not a good idea to use an external oscillator, use the on board oscillator circuit and get the crystal part right. The PLL/Oscillator supply on the chip is critical. The digital part supplies CLKOUT where MCK should be routed to (software mode) and is also very important.
But seriously, I do not want to debate SPDIF receivers. Pointless.
Thor
Non of this relevant to the TDA1541.
Provisional.
Actually using the 74HC40105 can easily make a 64 Bit delay chain with taps at 16/32/48 and 64 Bit... That is most that is needed already.
Going up from 192kHz has higher HD, you are pushing the speed of components. As there are no valid recordings in 8 X PCM there is nothing to listen to. Mind you, after the oversampling filter you already have a mess, why waste such a nice as a TDA1541 on that? But if you must, the correct way to do 8 X with TDA1541 is to use two IC's time multiplexed.
More here:
https://www.bramjacobse.nl/wordpress/?p=2834
To replace CXD1244 a CPLD/FPGA probably makes a lot of sense. It would be trivial to extend this to running 4 or even 8 TDA1541 this way.
For 1 X run all in parallel, 2 X split into two backs, 4 X split into 4 banks and so on. I have done this for other DAC's (TI "advanced segment"), the principle is the same.
Thor
Some more SPDIF RX tests from Japan and the Wayback Machine. I remembered this but could not find this:
https://web.archive.org/web/2016031...y.com/data/yohine/dac/jitter_measurement.html
Again, I don't want to debate these, but @bohrok2610 rightly remarked that real data is preciously rare.
Thor
For someone not wanting to debate SPDIF receivers you debate a lot about SPDIF receivers 🙂
Th gentlemen measuring the ICs in your link states that test circumstances differed between chips. There were other measurements showing WM8804/5 having way less than its datasheet value of 50 ps of jitter and that is was also better than DIR9001 but I forgot where. CS8412 was about 250 ps best case.
Anyway spilt milk, anyone with working ears quickly noticed WM8804/5 to be superior. Today one must be glad to find an SPDIF receiver at all it seems. For an inferior dinosaur interface SPDIF lives pretty long 😀
Th gentlemen measuring the ICs in your link states that test circumstances differed between chips. There were other measurements showing WM8804/5 having way less than its datasheet value of 50 ps of jitter and that is was also better than DIR9001 but I forgot where. CS8412 was about 250 ps best case.
Anyway spilt milk, anyone with working ears quickly noticed WM8804/5 to be superior. Today one must be glad to find an SPDIF receiver at all it seems. For an inferior dinosaur interface SPDIF lives pretty long 😀
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