While hitting a brick wall with the Tian probe, I went chasing rabbits down the thermal compensation hole.
Totally convention EF BJT amp. ( My "Reasonable" amp as described in my protection thread) Physically I would connect the bias servo transistor to one of the outputs. SOP.
OK, I add .step temp 20 125 5 to the schematic and run a DC operating point analysis. I then plot the current through one of the output emitters.
As expected, it climbs from my static set point of 85mA to 220 mA. it does level off at about 120 degrees.
Now I look at the voltage on the output base. As it should, it is decreasing. So as the servo heats up, it does decrease the bias voltage.
That leads to lots of questions.
Assumption is I do not have enough "gain" in the servo and am under-compensating. Yes?
I would want it to drift up just a bit, as too high buy a little is not as bad as too low. Yes?
How good do I expect to get it? Within 100%? 50%?
How do I select which components are getting hot? As it is everything is Yes?
Realistically, most of the amp will be pretty stable. Only the drivers and outputs would be heating up much. Sow do I simulate this?
OnSemi datasheet only mentions SOA plot based on 200 degrees C die. Nothing else. How do I determine what run-away is? The fact that the bias current levels off?
Totally convention EF BJT amp. ( My "Reasonable" amp as described in my protection thread) Physically I would connect the bias servo transistor to one of the outputs. SOP.
OK, I add .step temp 20 125 5 to the schematic and run a DC operating point analysis. I then plot the current through one of the output emitters.
As expected, it climbs from my static set point of 85mA to 220 mA. it does level off at about 120 degrees.
Now I look at the voltage on the output base. As it should, it is decreasing. So as the servo heats up, it does decrease the bias voltage.
That leads to lots of questions.
Assumption is I do not have enough "gain" in the servo and am under-compensating. Yes?
I would want it to drift up just a bit, as too high buy a little is not as bad as too low. Yes?
How good do I expect to get it? Within 100%? 50%?
How do I select which components are getting hot? As it is everything is Yes?
Realistically, most of the amp will be pretty stable. Only the drivers and outputs would be heating up much. Sow do I simulate this?
OnSemi datasheet only mentions SOA plot based on 200 degrees C die. Nothing else. How do I determine what run-away is? The fact that the bias current levels off?
Hi,
Linesource helped me with this.
Have a look at the picture from post nr15. I added a parameter in the component name. The result I get seemed logical.
http://www.diyaudio.com/forums/soli...-scratch-low-nfb-fet-front-end-bjt-ops-2.html
Linesource helped me with this.
Have a look at the picture from post nr15. I added a parameter in the component name. The result I get seemed logical.
http://www.diyaudio.com/forums/soli...-scratch-low-nfb-fet-front-end-bjt-ops-2.html
All SOAR are for 25 degrees C and must be reduced to actual die / junction temp accordingly. You have to calculate the dissipation which does not occur at full power but around 1/2 full power then calculate the junction temp . Then reduce the SOAR according to the junction temp.
Makes sense. Not easy. If I understand it, I need more compensation that a single servo transistor. So I added a diode to it's emitter that would be connected to another output. Too much, so I bypass it with a resistor.
Now, It says I drift over-bias a while, then back off if I get really hot so I don;t go into runaway.
I set two temp parameters, one {s} for stable I tagged all silicon except the outputs and servo/diode. The second {t} for the step of 20 to 200.
I then plot the current through an output Re.
Now, It says I drift over-bias a while, then back off if I get really hot so I don;t go into runaway.
I set two temp parameters, one {s} for stable I tagged all silicon except the outputs and servo/diode. The second {t} for the step of 20 to 200.
I then plot the current through an output Re.
I was only pointing out the data sheet is useless in this question.
It clearly states it's plot is for a junction temp of 200, not room temp.
I know how to do the T - sims on my OPS's.
BUT , for instance ... the "badger" will simulate as overcompensated.
LT lies !!
So , I use the simulator just to get the general idea of how a circuit
will behave thermally. To truly compensate , one HAS to experiment
on the real device.
I've found some of the models I have DO NOT even have the thermal info.
The ones that do , are often highly inaccurate. 🙁
PS - A Vbe device in a higher gain group will have a much higher tempco
than one in a lower gain group. You can trim tempco by just changing devices.
For example , a typical EF2 is "happy" with a mje350 or BDxxx ,
most EF3's specify a toshiba "Y" .
OS
BUT , for instance ... the "badger" will simulate as overcompensated.
LT lies !!
So , I use the simulator just to get the general idea of how a circuit
will behave thermally. To truly compensate , one HAS to experiment
on the real device.
I've found some of the models I have DO NOT even have the thermal info.
The ones that do , are often highly inaccurate. 🙁
PS - A Vbe device in a higher gain group will have a much higher tempco
than one in a lower gain group. You can trim tempco by just changing devices.
For example , a typical EF2 is "happy" with a mje350 or BDxxx ,
most EF3's specify a toshiba "Y" .
OS
I find it very easy to thermally comp an EF2. EF3's are a lot more difficult - just two more junctions and the problems seem to multiply up.
I also tried to sim in LT, but could not get it to match reality. This is a case I think where LT spice is ok to check if the circuit is functioning, but from there to simming a practical set-up is a huge step - lots of thermal gradients, Tj to Ambient is often not well known or characterized. I decided the best way forward was to try something that could be adjusted easily.
This is where I started out with this issue - ending up finally with the NTD solution described below the link. The main point I found is to have 2 ideal OPS bias current intercept points (a 'zero' and a 'span' in instrumentation speak)
http://hifisonix.com/wordpress/wp-c...on-for-Audio-Amplifier-EF-Triples-V1.0231.pdf
For the e-Amp, I used a conventional 2 transistor bias spreader, and then augmented this at high temp with a 10k NTD plus a series resistor network. I used a 1206 SMD device located close to one of the OP collector leads - cheap at about 50c IIRC from Mouser).
For set-up, I replaced the series resistor with a 20k pot set to 10k.
I set the OPS bias at c. 25 dec C, drive the amp at 1/3 power for about 1 hour so the heatsinks get to 50c (I am using the biggest Modushop Chassis - huge heatsings). Then I trimmed the pot to get the correct bias. Switch off, remove and measure the pot and then put the same value on the board as the pot measured.
This then gives two ideal bias intercept points - one at about 15 deg C and the other at about 50 deg C. The reason the lower intercept point is not at the original ~25C cal point is that when you make the pot adjustment at the high temp, you actually push the first intercept point down from 25 C to a lower temp. The NTD series resistor value will be fixed for the same mechanical (and therefore thermal) configuration - so its also perfect for a production type amplifier.
This is much easier than trying to get a conventional spreader to track 6 Vbe junctions over the full operating temp of the amp. I've seen other schemes that use additional Vbe junctions - I think those would also offer an improvement. Thermal track only sorts the power device junction temps out - the pre-driver and driver still need comp. The other issue of course is that the Vbe slope is linked to the device current density, so just assuming -2.2mV/C might not be good enough.
I use a BC847C as the primary temp sensor - coupled to the collector lead of one of the OP devices with a small glob of thermal grease.
BTW, you can also add more NTD's and have multiple ideal bias setting intercept points - I found 2 is ok though.
I also tried to sim in LT, but could not get it to match reality. This is a case I think where LT spice is ok to check if the circuit is functioning, but from there to simming a practical set-up is a huge step - lots of thermal gradients, Tj to Ambient is often not well known or characterized. I decided the best way forward was to try something that could be adjusted easily.
This is where I started out with this issue - ending up finally with the NTD solution described below the link. The main point I found is to have 2 ideal OPS bias current intercept points (a 'zero' and a 'span' in instrumentation speak)
http://hifisonix.com/wordpress/wp-c...on-for-Audio-Amplifier-EF-Triples-V1.0231.pdf
For the e-Amp, I used a conventional 2 transistor bias spreader, and then augmented this at high temp with a 10k NTD plus a series resistor network. I used a 1206 SMD device located close to one of the OP collector leads - cheap at about 50c IIRC from Mouser).
For set-up, I replaced the series resistor with a 20k pot set to 10k.
I set the OPS bias at c. 25 dec C, drive the amp at 1/3 power for about 1 hour so the heatsinks get to 50c (I am using the biggest Modushop Chassis - huge heatsings). Then I trimmed the pot to get the correct bias. Switch off, remove and measure the pot and then put the same value on the board as the pot measured.
This then gives two ideal bias intercept points - one at about 15 deg C and the other at about 50 deg C. The reason the lower intercept point is not at the original ~25C cal point is that when you make the pot adjustment at the high temp, you actually push the first intercept point down from 25 C to a lower temp. The NTD series resistor value will be fixed for the same mechanical (and therefore thermal) configuration - so its also perfect for a production type amplifier.
This is much easier than trying to get a conventional spreader to track 6 Vbe junctions over the full operating temp of the amp. I've seen other schemes that use additional Vbe junctions - I think those would also offer an improvement. Thermal track only sorts the power device junction temps out - the pre-driver and driver still need comp. The other issue of course is that the Vbe slope is linked to the device current density, so just assuming -2.2mV/C might not be good enough.
I use a BC847C as the primary temp sensor - coupled to the collector lead of one of the OP devices with a small glob of thermal grease.
BTW, you can also add more NTD's and have multiple ideal bias setting intercept points - I found 2 is ok though.
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The SOA published by the manufacturers tells us that Tc is held @ 25°C and that Tj is allowed to rise to maximum, i.e. Tjmax.
That difference from Tc to Tjmax maximises the heat flow from junction to backplate. The heatsink has to then get rid of that maximised heat flow with the intervening Thermal Resistance of the contact interface while still maintaining Tc at 25°C.
They also tell us to de-rate twice. Once for Tc >25°C and for Vce > published knee voltage.
That difference from Tc to Tjmax maximises the heat flow from junction to backplate. The heatsink has to then get rid of that maximised heat flow with the intervening Thermal Resistance of the contact interface while still maintaining Tc at 25°C.
They also tell us to de-rate twice. Once for Tc >25°C and for Vce > published knee voltage.
OS,
Good tips. Modeling is informative, but I gathered some time ago, you have no choice but to prototype. The model helps to put the scope of the problem into perspective. It helps show us what we WANT it to do.
What I don't know is what the working profile of the drivers will be. My current plan was to have them on their own heat sink, so I am trying to guess two different curves. I can see why M.I. suggested L-MOSFETS for drivers. Only 4 Vbe, but different. I have resisted an output tipple as by the modeling, I am "good enough" with only 2 stages. I can meet the output base currents OK for such a small amp. This being my "Reasonable" not ultra, if it models at .001 and comes out in real life only 10 times worse, it will have exceeded my goals for learning.
So, what I should model is something easy to modify. When I lay out the board, I'll leave spaces for several more parts. Until its in the chassis, on a shelf, playing real music, we just don't know.
Bonsi
Your link crashes my Acrobat.
Several other ideas to digest. By "conventional two transistor", I can think of about four configurations, and I think Cordell shows more. Which are you using?
Andrew,
Yes, it SHOULD say as you suggest, but my data sheet does not for these outputs. It only has a single SOA plot (log at that) specified at 200 C. I sure hope I never am anywhere near that hot. In my old lab days we had two rules:
#1 Every 10 degrees was half life.
#2 135 degrees was asking for trouble. It was our corporate maximum spec. Transistors are a lot happier at 80. That might suggest 40 to 80 as a good target operating range to design to.
Another observation: As we no longer require the FTC preconditioning spec, I see what is specified as "100W" amplifiers with enough heat sink for a preamp power supply, where my old Hafler 120 is many times as massive. It could met the spec. It's spec is for 60W, same as my design, but it has over 3 dB overhead. Marketing exec's. today would never let that pass. One more thing to change when I get appointed dictator for a day. 😀
Good tips. Modeling is informative, but I gathered some time ago, you have no choice but to prototype. The model helps to put the scope of the problem into perspective. It helps show us what we WANT it to do.
What I don't know is what the working profile of the drivers will be. My current plan was to have them on their own heat sink, so I am trying to guess two different curves. I can see why M.I. suggested L-MOSFETS for drivers. Only 4 Vbe, but different. I have resisted an output tipple as by the modeling, I am "good enough" with only 2 stages. I can meet the output base currents OK for such a small amp. This being my "Reasonable" not ultra, if it models at .001 and comes out in real life only 10 times worse, it will have exceeded my goals for learning.
So, what I should model is something easy to modify. When I lay out the board, I'll leave spaces for several more parts. Until its in the chassis, on a shelf, playing real music, we just don't know.
Bonsi
Your link crashes my Acrobat.
Several other ideas to digest. By "conventional two transistor", I can think of about four configurations, and I think Cordell shows more. Which are you using?
Andrew,
Yes, it SHOULD say as you suggest, but my data sheet does not for these outputs. It only has a single SOA plot (log at that) specified at 200 C. I sure hope I never am anywhere near that hot. In my old lab days we had two rules:
#1 Every 10 degrees was half life.
#2 135 degrees was asking for trouble. It was our corporate maximum spec. Transistors are a lot happier at 80. That might suggest 40 to 80 as a good target operating range to design to.
Another observation: As we no longer require the FTC preconditioning spec, I see what is specified as "100W" amplifiers with enough heat sink for a preamp power supply, where my old Hafler 120 is many times as massive. It could met the spec. It's spec is for 60W, same as my design, but it has over 3 dB overhead. Marketing exec's. today would never let that pass. One more thing to change when I get appointed dictator for a day. 😀
Are you sure?
Surely, an SOA plot specified at 200 C means
1) A TO3 device
2) Zero power output.
Doesn't it?
tvrgeek try this:-
http://hifisonix.com/wordpress/wp-content/uploads/2011/03/The_e-Amp_V2.03.pdf
I'm using a conventional CFP pair - you can see it in the circuit in the above doc.
Here's another doc about temp comp also
Temperature-Compensation-for-Audio-Amplifier-EF-Triples-V1.023[1] | hifisonix.com
http://hifisonix.com/wordpress/wp-content/uploads/2011/03/The_e-Amp_V2.03.pdf
I'm using a conventional CFP pair - you can see it in the circuit in the above doc.
Here's another doc about temp comp also
Temperature-Compensation-for-Audio-Amplifier-EF-Triples-V1.023[1] | hifisonix.com
It does not tell you that.
It specifies Tc=25°C and allows Tj to rise to Tjmax.
The de-rating that the manufacturer tells you to apply is for Tc>25°C
I see you consider all junctions are at the same temperature, which is not true.
The Output BJT temp is at a much higher temp than the heat sink, while the Vbe multiplier BJT junction temp is a bit higher than the heat sink.
Furthermore: The difference between Output BJT junction temp and Vbe multiplier BJT junction temp depends a lot of the output power.
The power in the Output transistor varies a lot with the amplifier output power while the power in the Vbe multiplier is about constant.
These temps can be calculated for a given output power for steady state.
What goes on with power transients becomes much more involved.
A topic adressing some of the issues.
http://www.diyaudio.com/forums/software-tools/151548-ltspice-how-model-temperature.html
If you have any idea better than opening TO-3 cases (these happen to be TO3-P so I can't even to that) and using an IR ccd to look at the die surface, let me know. In the mean time, I am trying to understand how to use SPICE to give me some idea on how it works.
I know you can't run my model as I integrate all my transistors into my library file, so I just posted the PDF. What it shows is if I find some middle ground on the % of compensation, I can get the bias to increase by only about 50% before it levels off. Never goes lean, never runaway. A target for the real world.
I set only the outputs and servo as "{t}", all the rest as "{s}" fixed. Only {t} am I stepping. The drivers will have some variance due to signal even though not as much being class A. I plan on even more selective settings. Maybe setting the temp change as half of the outputs. This is to figure out how it all works.
This is only a sim to understand how it works and pick an architecture. Values and adjustments can only be done on the real parts. A sim is only as good as the model, and as I have already established OnSemi does not even have traditional SOA charts for this part, why should I trust their model?
Good reads here. When I started this educational project, I sort of suspected this was an area that needed more understanding.
Pretty fancy amp mentioned here.
An estimation of the chip-junction temperature, TJ, can be obtained from the following equation: TJ = TA + ( R θJA × PD )
where: TA = ambient temperature for the package ( °C )
R θJA = junction to ambient thermal resistance ( °C / W )
PD = power dissipation in package (W)
Thermal resistance - Wikipedia, the free encyclopedia
BJT Data sheets give: Junction to case thermal resistance.
Insulator pad or thermal grease has some thermal resistance.
Heatsinks data give: Heatsink to ambient thermal resistance.
Transient temperature simulation needs two more parameters:
Junction thermal capacitance and Heatsink thermal capacitance.
Here is a good source: http://sound.westhost.com/heatsinks.htm
where: TA = ambient temperature for the package ( °C )
R θJA = junction to ambient thermal resistance ( °C / W )
PD = power dissipation in package (W)
Thermal resistance - Wikipedia, the free encyclopedia
BJT Data sheets give: Junction to case thermal resistance.
Insulator pad or thermal grease has some thermal resistance.
Heatsinks data give: Heatsink to ambient thermal resistance.
Transient temperature simulation needs two more parameters:
Junction thermal capacitance and Heatsink thermal capacitance.
Here is a good source: http://sound.westhost.com/heatsinks.htm
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Trying to get a conventional spreader to comp an EF3 accurately in my view is not possible. Too many variables thermally, electrically and then you have the dynamic of the program material on top of that.
I like to think about the problem differently.
If you design the comp circuit to intercept the ideal bias current in more than one position on the temperature axis, you get. Much better tracking as a result.
The e-amp only used 2 intercepts. If you had 3 or 4' the errors would be very small.
In a previous life I designed thermocouple signal conditioners and multi- slope linearizers (using hardware break points and later software versions). Quite easy to linearizers a TC to within 0.5 % using these techniques. And, they are also applicable to temp comp in audio amps.
Time for me to start to think about an 8 pin MCzu solution - self calibrating. Might make an interesting project for the forum.
I like to think about the problem differently.
If you design the comp circuit to intercept the ideal bias current in more than one position on the temperature axis, you get. Much better tracking as a result.
The e-amp only used 2 intercepts. If you had 3 or 4' the errors would be very small.
In a previous life I designed thermocouple signal conditioners and multi- slope linearizers (using hardware break points and later software versions). Quite easy to linearizers a TC to within 0.5 % using these techniques. And, they are also applicable to temp comp in audio amps.
Time for me to start to think about an 8 pin MCzu solution - self calibrating. Might make an interesting project for the forum.
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