BTW, would like to recommend to try reclocking after the FPGA, and see if any audible difference. Maybe even with an isolator before the reclocker. IMHO this converter can sound pretty darn good, quite good for real-time conversion. Assuming a little cleaning up of the I2S signals out of the FPGA, best offline conversion found so far is maybe only a little bit better. On the downside for offline conversion, it can be pretty slow and file sizes for DSD256 can be rather large 🙂
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@Mark
I am not able to reproduce the loud pop noise behaviour.
Possible reason: I use a reworked design for Amanero circuit, in which both oscillators have different LT3042 PSUs, so clock selector pins from Amanero's CPLD actually enable/disable LT chips, too. In this case the clock domain is switched slower (a few ms), even if I used "fast startup" circuit for LTs. Before "fast startup" confirguration for LTs, (about 55 ms start time), Pjotr's original top.bit file didn't worked right for me, as I got hisss noise at every clock domain changes.
Another reason could be the DAC I used for tests, Sygnalist DSC2 with 10k:10k trafos output and digital isolator at its input. Anyway, tried all SR switch combination, but no any pop noise.
I am not able to reproduce the loud pop noise behaviour.
Possible reason: I use a reworked design for Amanero circuit, in which both oscillators have different LT3042 PSUs, so clock selector pins from Amanero's CPLD actually enable/disable LT chips, too. In this case the clock domain is switched slower (a few ms), even if I used "fast startup" circuit for LTs. Before "fast startup" confirguration for LTs, (about 55 ms start time), Pjotr's original top.bit file didn't worked right for me, as I got hisss noise at every clock domain changes.
Another reason could be the DAC I used for tests, Sygnalist DSC2 with 10k:10k trafos output and digital isolator at its input. Anyway, tried all SR switch combination, but no any pop noise.
Thanks for all the info 🙂
In the case here the FPGA output is going to be isolated, FIFO buffered, and reclocked (so have to use top.bit). Sounds quite a bit better that way, is why. At least it does with with a good enough dac to show the difference. Probably it will be possible to fix the pop noise problem in some downstream circuitry. Also I am using I2SoverUSB which I like better than Amanero. Made a little board to interface it with the Simple DSD Converter board, including inverting the DSD_ON signal.
However, what you did and what I'm working on are probably not what everyone is going to be able to do. If other folks have the same problem, don't know if there will be a solution for them.
EDIT: One more comment, instead of using two LT3042's it might work better to keep both clocks running all the time and switch them with two NB3L553 clock buffers. The buffers are very low phase noise and the clocks might like not driving long lines and or capacitive load mismatching. They will work either way of course, but maybe less overall jitter if buffered. If trying that, I like 805 smd film bypass caps rather than X7R. Sounds better to me for clocks and for buffers.
In the case here the FPGA output is going to be isolated, FIFO buffered, and reclocked (so have to use top.bit). Sounds quite a bit better that way, is why. At least it does with with a good enough dac to show the difference. Probably it will be possible to fix the pop noise problem in some downstream circuitry. Also I am using I2SoverUSB which I like better than Amanero. Made a little board to interface it with the Simple DSD Converter board, including inverting the DSD_ON signal.
However, what you did and what I'm working on are probably not what everyone is going to be able to do. If other folks have the same problem, don't know if there will be a solution for them.
EDIT: One more comment, instead of using two LT3042's it might work better to keep both clocks running all the time and switch them with two NB3L553 clock buffers. The buffers are very low phase noise and the clocks might like not driving long lines and or capacitive load mismatching. They will work either way of course, but maybe less overall jitter if buffered. If trying that, I like 805 smd film bypass caps rather than X7R. Sounds better to me for clocks and for buffers.
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I have hiss at right channel when playing native DSD files when pcm2dsd simple modulator pass trought native DSD.
Also still problems playing native DSD512 files when pcm2dsd simple modulator pass trought native DSD.
Also still problems playing native DSD512 files when pcm2dsd simple modulator pass trought native DSD.
Does DSD file playback work okay if pcm2dsd is removed from the circuit, and only Amanero is used?
What does the wiring look like that connects Amanero -> pcm2dsd -> dsd dac look like? Do have have a clear pic?
Any chance you have a scope?
What does the wiring look like that connects Amanero -> pcm2dsd -> dsd dac look like? Do have have a clear pic?
Any chance you have a scope?
There is any difference between DSF & DFF both DSD files?
Native DSD64 DSF files are all noise DFF noise free, DSD128 DSF & DFF are both noise free, DSD256 DSD are noise free.
Native DSD64 DSF files are all noise DFF noise free, DSD128 DSF & DFF are both noise free, DSD256 DSD are noise free.
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The MCLK signal should also be a coax. The coax cables should be rated at 50-ohms, are they? How long are the coax cables?
Unfortunately a 20MHz scope isn't that good for digital. 100Mhz, barely good enough. 200Mhz would be nice. Otherwise its very hard to tell if the clock edges look reasonable.
Unfortunately a 20MHz scope isn't that good for digital. 100Mhz, barely good enough. 200Mhz would be nice. Otherwise its very hard to tell if the clock edges look reasonable.
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Okay. MCLK should be in a coax too. Does the sound change at all if you move the coax cables around a little while playing music? What if they are close together, versus spread apart from each other? Any difference in sound?
Of course, best thing would be wider bandwidth scope.
Of course, best thing would be wider bandwidth scope.
Changed the MCLK for coax 50 ohms also. Time to listen.
With shipping the new 200mHz scope is expensive circa 500€ for a retired at work man like me.
With shipping the new 200mHz scope is expensive circa 500€ for a retired at work man like me.
True, scopes are kind of expensive. Unfortunately, they are needed if doing much work with modern dacs. Possibly a used one, say, maybe 100MHz?
May I ask what your best line conversion is sofar ? What program/settings do u use ?
Just a short parenthesis here: DSD streams are already aligned with ODDR2 primitives, as olo111 said in the first post.
We like PCM-DSD Converter. Settings are FIR filter, and DSD256. https://pcmdsd.com/Software/PCM-DSD_Converter_en.html