I can't speak by absolutes...
but i found this conversion less "refined" than the DSD'it from ppy, and far less than the Hqp.
convenience and costs are top notch
puredsd.ru and then check out DSD'it. an OpenHardware project from Pavel.
IME his implementation is very close to what roon is capable regarding PCM->DSD conversion.
Compared to HQP with latest EC modulator there's no battle (at least, for me and my ears).
Sure
HQP SDM :
HQPlayer (SDM output) with ADSDM7EC DSD128 sinc-M
BeagleBoneBlack with Pure firmware and BBBReclk (puredsd.ru) (NDK-SA clocks 45.158,4 / 49.152) [output reclocked]
TTL->LVDS converter to send data over HDMI cable
LVDS->TTL receiver
IanCanada McFIFO+McDualXO (TWTMC DRIXO 22.579,2 / 24.576)
DSC St!ck's (dual mono)
DSD'it :
HQPlayer (PCM output) sinc-M 44.1/48Khz
BeagleBoneBlack with Pure firmware and DSD'it (puredsd.ru) (NDK-SA clocks 45.158,4 / 49.152). [output reclocked]
TTL->LVDS converter to send data over HDMI cable
LVDS->TTL receiver
IanCanada McFIFO+McDualXO (TWTMC DRIXO 22.579,2 / 24.576) [output reclocked]
DSC St!ck's (dual mono)
PCM2DSD FPGA board:
HQPlayer (PCM output) sinc-M 44.1/48Khz
BeagleBoneBlack with Pure firmware and BBBReclk (puredsd.ru) (NDK-SA clocks 45.158,4 / 49.152). [output reclocked]
PCM_2_DSD_Board with gating added for compatibility
TTL->LVDS converter to send data over HDMI cable
LVDS->TTL receiver
IanCanada McFIFO+McDualXO (TWTMC-DRIXO 22.579,2 / 24.576 doubled with TWTMC-DBM) [output reclocked]
DSC St!ck's (dual mono)
Sure
Thank you very much. Good job
We never said it directly but did say pcm2dsd was made for Amanero. Amanero has MCLK 22/24MHz. And for these clocks it was done (calculations etc). And with BBBReclk we probably have MCLK 45/49 MHz. It's hard to predict how it will work ...
Is not "probable"... i have written down, i am using 45/49Mhz on that thing.
If you think it will perform best with lower freq i can swap the oscillators on the bbbrclk with a 22/25mhz ndk-sa set
(I only need to find them again )
To make them work with the pure firmware i Just need to change couple of variables.
If you think it will perform best with lower freq i can swap the oscillators on the bbbrclk with a 22/25mhz ndk-sa set
(I only need to find them again
)To make them work with the pure firmware i Just need to change couple of variables.
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Already know about that one. It is designed to be low cost and pretty good. Something like that designed to be the best possible might be another matter.
The Chinese board can be improved significantly by putting a good LDO regulator on the back of the board (ground plane) and use it to power AK4137, and to power the A/B switch logic chip (mux). That, and sending AK4137 a copy of the dac clock (instead of using the built-in clocks) can make it much better. Send the USB board a copy of the dac clock too and things get better yet. Main problem at that point is there is only one AK4137 when it actually takes two of them to do DSD256 correctly.
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I know, you wrote
Everything was written for 22/24MHz and tested with it. Or maybe do it differently, test pcm2dsd behind the IanCanada McFIFO + McDualXO.
Sorry I'm a bit greedy.
Because of the same work, same timing, and same parts ordering, I want it to be the best I can.
Then there is one question: if I Pull-up DSD_En on the Amanero header onto Vcc, so I2S will passthrough to DSC header output!?
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I know, you wrote
Everything was written for 22/24MHz and tested with it. Or maybe do it differently, test pcm2dsd behind the IanCanada McFIFO + McDualXO.
can't use after the mcfifo because the output is reclocked and since your converter outputs dsd512, i needed 45/49 mhz, indeed i have used a doubler on the sine 22/24. so here i have again higher frequency, but is used just for reclocking.
if the clock that matters is what is feed it, then i must change the mclk at the source.
The fifo is isolate clock domains