Sorry Samuel, but the En vs. Id curve in the datasheet you mentioned follows exactly the model I just decribed. If you mean the Noise Figure vs. Id, that's completely different story. For the use of audio, the Noise Figure (so including the effect of RG, the source impedance) is pretty much irrelevant. Noise Figure has only a remote connection to the input referred noise, or SN ratio. In the datasheet, the Noise Figure variation with Id is flat simply because the source impedance (1kohm) noise of about 4nV/rtHz completely hides any device dependent noise.
Nop. It increases with square-root of Id; see e.g. exp05.pdf equation 5.3 or again 2SK170 datasheet (Yfs goes from 15 mS to 40 mS with Id from 1 mA to 10 mA). That's the key point where your analysis fails.
gm is ~proportional to collector current for BJTs. That's why there is a fixed proportional relationship between GBW and slew-rate for opamps with undegenerated BJT input stage. JFET opamps are generally faster because this relationship does not hold; we can increase the drain current without a proportional increase of the compensation capacitor.
For low noise amplifiers this is a pitty because we need large gm for low second-stage contribution. Hence the rule holds: lowest possible Id is best.
Samuel
See 2SK170_en_datasheet_071101.pdf, page 3, middle row, left column. Voltage noise converges to 0.8 nV/sqrt(Hz) above Id = 3 mA and not towards zero as your formula suggests.
Samuel
No, no and no. I don't have the time to put here the entire exact noise theory of JFET devices, you'd be better reading a real book on JFET noise (I can make a few recommendations). Enough to say that for small source degeneration, the transconductance is proportional to Id (because Id is close to Idss and therefore Id*Idss~Id^2, just do the Taylor series, etc...). For larger degenarations, the whole calculation fails, because the source resistor will dominate the noise, anyway. The noise saturation is again the effect of the source degeneration (decreasing Id) rather than an intrinsic device effect. Bottom line, noise decreases as SQRT(1/gm) and you'd better run the JFETs as close as possible to Idss to maximize the transconductance and minimize the noise.
Let's agree to disagree, I am anyway over and out on this topic.
I think syn08 is correct, as it is fairly standard to think that thermal noise is the major noise contributor in a jfet. On the other hand running the jfet near Idss and at high Vds will increase gate leakage current (see last plot in the 2sk170 data sheet) and that could become a significant source of noise in conjunction with Rg. Not only, but it will also heat up the jfet and so even voltage noise goes up. Still, I know nothing but the most trivial things about this.
Samuel, you mentioned replacing R3 with a CCS, or I didn't understand you correctly? In any case, you mentioned that the concern would the noise of the CCS. Just for laughs I replaced R3 with two paralleled J310 jfets (each Idss of about 46mA), with a 17 ohms resistor from source to gate. Simple CCS, but with various shortfalls. Had to try a few resistors to get the 17R value. The results was that the measured noise now is about 0.43nV/rtHz. This still with batteries.
Did you try to locally filter the B+ with RC or Cmult for the first stage yet? Maybe there is a little more SNR to gain, or its OK for you?
Not yet, I had little time today for this and was eager to try the ccs, but I definitely will try it next. Aiming for tomorrow morning when I get there, though I have a loaded day. But it should be quick.
Correct. A CCS leads to best PSRR and lowest second-stage noise contribution because--as you mentioned--it maximises first stage gain. A CCS has its own noise contribution but JFET-based ones are generally speaking pretty good.
Great. Glad I'm not *that* stupid after all 😉.
Samuel
BTW, what was the total drain current with the resistor and what's it now with the CCS?
And you might want to recheck the gain of the preamp (I've noted that you increased the feedback resistor value to compensated finite loop gain).
What I didn't mention: with the CCS the servo does not work as intended. It's return point should be chosen differently.
Samuel
And you might want to recheck the gain of the preamp (I've noted that you increased the feedback resistor value to compensated finite loop gain).
What I didn't mention: with the CCS the servo does not work as intended. It's return point should be chosen differently.
Samuel
I just looked up an IEEE paper by Scott Wurcer where he mentioned the presence of gate series resistance in JFETs and according noise contribution and deviation from Ziel's estimate. Scott, do you have any idea what this resistance might be in a device like the 2SK170 or BF862?
Samuel
Samuel
I am having troubles understanding how this drain CCS circuit bias is working. The balance between the K170 drain current and the CCS current is source/sinking through the opamp feedback resistor. The servo helps keeping the output at zero, but only so much. It cannot also source/sink current, but only set the opamp common mode voltage so that the output is at zero.
It seems to me that this bias method is looking for trouble. It needs at least careful and fine adjustment of the CCS current (to match the K170 drain current) and temperature, etc... behaviour is questionable.
Yes, that was my comment about the servo return point. I think in his circuit the CCS gets saturated by the servo, acting as a medium-value resistor rather than true CCS. But with an appropriate servo connection it could be made to work.
Samuel
100% agreed, with one ammendment: the concept of "saturation" when it comes to JFETs is different to the bipolar devices satuaration. For bipolars, "saturation" is associated with Vce<Vcb-Vbe, while for JFETs, "saturation" is usually associated with Vds>2*Vt (so the normal operation area). What you are describing is in fact the JFET CR (controlled resistor) mode, that is, for small Vds the JFET acts between source and drain as a gate controlled resistor.
There might be a servo based solution, but out of the bat I don see anything simple that would not affect the noise. I think AC coupling the opamp common mode to the supply as in HPS5.1 is the simplest solution to increase the PSRR to -50dB in the audio band.
Yes I noted that it is difficult to set the current to the right value, and noticed that enough temperature variation will throw it off the right course.
For me it was just something to try and see if the noise would indeed go down with a CCS.
Aha, indeed it doesn't work as a very good CCS, which helped in this case. The part I left out from my report is that I had developed a better CCS (in the simulator) and with that setting the right current was even more problematic, and so was the temperature sensitivity.
One thing I want to mention to both of you. Even with the servo loop out of the equation the CCS current seems to have to be set very precisely for the highest gain/psrr, and the temperature sensitivity is still there. This is not a good solution, but I had to try it for myself and see what happens.
Edit: Samuel, the overall gain has increased a tiny bit, but I still divided the measured 430nV/rtHz to 1000 to keep things simple in the discussion.
You're misunderstanding things. The problems you mention occur because the servo does not work--in essence the CCS has to match the total drain current of the input JFETs exactly without the servo. If you had a properly working servo the value of the CCS would be much less critical.
A noninverting servo connected through a resistor to the inverting opamp input should work and have similar noise contribution. But I'd need to look at it into more detail.
Samuel
Set aside the noise impact of the resistor, that would be a loop gain killer (appears AC parallel with the CCS).
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