Simple 60dB discrete low noise amplifier (lna)

iko

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Joined 2008
No, potentially it won't stand the power.

I was worried about that but tried it anyway because I got nothing beefier here. It is getting hot, but it survived for now.

With that opamp follower you just spoiled the entire design (and the noise performance as well). The whole key is using the first low noise stage as a transconductance amp, and using the second stage very low input impedance (also shunting the opamp voltage noise!) the open loop gain is gm*R17, where gm~2*Id/Vt. The opamp current noise feeds R17 as well, but the noise voltage effect is very smal because a) it's a fet input opamp, noise currents are small and b) the equivalent resistor is divided by the opamp open loop gain.

That's too bad. I was hoping to use precision feedback resistors to trust the gain is as close as possible to 60dB so I can use this for measuring noise. Without the buffer the output comes out to be 59.6dB in simulation. I don't know how much the simulation can be trusted, but with the buffer the output shows 59.99 dB.

There is no point feeding the input stage (and referring the input to) -Vee. Instead, ground will do just fine.

Wanted to power it from two 12V batteries which seems to be too low for your exact circuit.

Scott, yes, Samuel is right. Thanks for the Wenzel amp suggestion, I've looked at it as I did at almost a dozen others. I like syn08's circuit best so far for what it promises and the design.

I just tested the first stage with a 50 ohm resistor across the input and the output shows as 8nV/rtHz at 2kHz on my HP 3585A, which seems to be the noise floor of the analyzer. Measured the gain to be approximately 44 times, so would that mean the input referred noise is about 0.18nV/rtHz?
 
I just tested the first stage with a 50 ohm resistor across the input and the output shows as 8nV/rtHz at 2kHz on my HP 3585A, which seems to be the noise floor of the analyzer. Measured the gain to be approximately 44 times, so would that mean the input referred noise is about 0.18nV/rtHz?

Short the input. Otherwise, 50ohm has 0.9V/rtHz x 44 = 40nV/rtHz at the output. Don't know what are you measuring, something is certainly wrong. I certainly doubt the 3585A has 8nV/rtHz floor noise. Looking at it's spec, it has -137dBm (~1uV in 50ohm) in 3Hz BW, this makes roughly 570nV/rtHz. Also corner frequency is 10KHz, pretty lame.
 
Edit: actually I modified the circuit a little more, to power it from two 12V batteries. Added a buffer after the first stage, seems to get closer to the theoretical 60dB this way. I happen to have a bunch of opa4134s on hand, so I'm planning to use one to cover the second stage, servo, and buffer.

With that opamp follower you just spoiled the entire design.

Indeed the follower is complete nonsense but the main problem is the biasing of Q2--D4 needs to go to ground, not VEE!

Samuel
 

iko

Ex-Moderator
Joined 2008
Indeed the follower is complete nonsense but the main problem is the biasing of Q2--D4 needs to go to ground, not VEE!
Samuel

Samuel, it's kind of you to point out mistakes. It would help even more to give an explanation. Or at least hints, if you really like the "tough teacher" role. But of course, nothing is required. I'm just saying that in general, those who know less than you guys who are well versed in design, can learn so much from your comments. I and I'm sure many othersdo appreciate your contributions, whether it means anything to you or not.
 

iko

Ex-Moderator
Joined 2008
I forgot the number but we had (now unreadable display) an HP SA that was 10Hz - 40MHz and had 7-8nV noise floor. It also had an IF offset so you could do Dick Heyser's swept frequency analysis directly.

When I short the input on my analyzer and use the noise level measurement button (and 3Hz BW) it reads about 8nV/rtHz. It should be adequate to measure the output noise of the preamp and then divide by the gain to get the input referred noise.
 
It would help even more to give an explanation.

My apologies for the short writing--I'm usually in a hurry that's why.

D4 needs to go to ground, not VEE!

As shown in your schematic the drain of the JFETs is negative w.r.t. the source--the transistors simply don't work that way. The source-drain voltage should be at or above 2x Vp so ~3 V for the 2SK170.

The follower is complete nonsense.

It's difficult to explain that further. The topology is arranged such that the input JFETs work as transconductance stage (i.e. voltage in--current out) and the second stage (formed by the first opamp) as integrating transimpedance stage (i.e. current in--voltage out). This has several advantages, e.g. so-called pole-splitting which improves the stability of the amplifier. With the added buffer this is completely messed up--I doubt it would work consistently if at all in real world.

If you don't understand a simulation result: don't believe it. You need to understand how the amplifier works before you put it in sim, otherwise you have no chance to judge the sim output. I believe that the low gain you're observed is simply a result of the wrong input stage biasing.

Samuel
 
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syn08 said:
Noise here counts only if you are looking at 0.2-0.3nV/rtHz.

I would still be interested why you think that Q5 (in your schematic) is particularly critical w.r.t. to voltage noise. Voltage noise in this transistor simply modulates the drain voltage of the input JFETs but does not directly add to the current fed to the second stage. Current noise is of some importance but above the 1/f region surely a second order term given reasonably high hFE.

A couple of other remarks for your circuit:

* What does R12/C17 do? It looks like they should somehow aid compensation but the impedance is negligible compared to R13 so have no influence.
* What's R9 for?

Samuel
 
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iko

Ex-Moderator
Joined 2008
I'll try to make sense of your comments, will go and read up on the transconductance amp; much appreciated!

As shown in your schematic the drain of the JFETs is negative w.r.t. the source--the transistors simply don't work that way. The source-drain voltage should be at or above 2x Vp so ~3 V for the 2SK170.

I put the operating point voltages on the schematic, should be fine, I think. Did you notice that I referred the input to Vee as well?

If you don't understand a simulation result: don't believe it. You need to understand how the amplifier works before you put it in sim, otherwise you have no chance to judge the sim output.
Samuel

I agree, this transconductance amp confused me greatly, so I need to do some more reading.
 

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I would still be interested why you think that Q5 (in your schematic) is particularly critical w.r.t. to voltage noise. Voltage noise in this transistor simply modulates the drain voltage of the input JFETs but does not directly add to the current fed to the second stage. Current noise is of some importance but above the 1/f region surely a second order term given reasonably high hFE.

A couple of other remarks for your circuit:

* What does R12/C17 do? It looks like they should somehow aid compensation but the impedance is negligible compared to R13 so have no influence.
* What's R9 for?

Samuel


The key is indeed the noise current ~SQRT(Ic/Beta) and beta "reasonable high" for a power device (given Icmax about 100mA and Vce about 15V). Power devices usually don't have much beta (and, as a result, low noise!) because the base is highly doped with impurities, and that's required for an improved SOA. The ZXT690 device is a very good compromise between power (it's in a DPAK case) beta (>400) and noise (Rbb=20ohm). You may want to do the math for replacing the ZXT690 with a 2N5551 with Icmax=600mA, Beta @100mA=30 and Rbb=100ohm and you'll notice how it will affect the noise.

R12/C17 is lead-lag compensation. For 60dB gain, it's marginally required, but for a gain of 40 (as I am using it in my RIAA head amp) is mandatory for stability. There, I am using 10ohm in series with 100nF.

R9 sets the open loop gain to gm*R9, where gm is the input stage transconductance.
 
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Wouldn't it be better to drive the greens from a high Vp Jfet or some other CCS to match their impedance better and make it less harmonic noise pick up potential for single ended connection? But you use a large filter cap on the base node OTOH.
 
Did you notice that I referred the input to Vee as well?

No, my bad. Perhaps that's actually a rather clever move--doesn't that allow you to make R13 (deisgnator from your schematic) larger without saturating Q2? That'd reduce noise somewhat.

The key is indeed the noise current ~SQRT(Ic/Beta) and beta "reasonable high" for a power device (given Icmax about 100mA and Vce about 15V). Power devices usually don't have much beta (and, as a result, low noise!) because the base is highly doped with impurities, and that's required for an improved SOA. The ZXT690 device is a very good compromise between power (it's in a DPAK case) beta (>400) and noise (Rbb=20ohm). You may want to do the math for replacing the ZXT690 with a 2N5551 with Icmax=600mA, Beta @100mA=30 and Rbb=100ohm and you'll notice how it will affect the noise.

Great that we agree on this. So why not just use a "Baxandall super pair" for the cascode? That'd reduce the base current noise contribution to entirely negligible levels.

R9 sets the open loop gain to gm*R9.

Sure, but what's the point of it? A "low global feedback" trap..?

Samuel