Signalyst DSC1

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#1,941
nautibuoy said:
I finally made some good progress with my DSC2(V2.5.2) build today ... Output section assembled using Lundahl LL1684 transformers
Click to expand...


Hi nautibuoy! Can you briefly compare Lundhal LL1684 sound with the "original" chinese yellow transformers?


I've a DSC2.5.2 dac equipped with yellow transformers and sound satisfies me a lot, I can describe it as organic without but no "fat", very good voice reproduction.


Now I've a pretty new DSC Stick assembly (build by Saint "Gionag" :spin:) that's a real beauty ... Output transformers are the V2 built by Ivan that's definitely better that the chinese one and overall DAC measurements overwhelm my DSC2.5.2 ... but sound is now really really precise

I mean, sound is perfect with perfect recordings, with less than perfect recordings, sound is still very good but with little too much of hiss on female voices

So, my first idea is to buy a pair of yellow chinese transformers and then mount on DSC Stick ...
My second idea is to buy a pair of Lundahl and do the same trick but due the cost of LL, first I need to grab feedbacks

Thanks in advance
 
#1,942
gionag said:
Well,
a little late on my self-imposed schedule.

Sticks are assembled and tested inside and out.

They are running fine, simple and exceptional.

Now its time to take care of the docs...
Click to expand...

Hello. Very nice design for your boards. Tell me in your circuit, as I understand it, DSD clk goes to the buffer and then to the registers, the rest of the DSD signals (inverse) go to the registers directly to the 19 pins? Are there any problems that the circuit for generating all signals for DSD (reclocking DSD clk, DSD L / DSD R and invert signals) are located at a distance on another board, does not the meaning of reclocking be lost? I am planning to put one 1G125 on the DSD ckl line, I think it will be enough. Thank
 
#1,943
alesoleg said:
Hello. Very nice design for your boards. Tell me in your circuit, as I understand it, DSD clk goes to the buffer and then to the registers, the rest of the DSD signals (inverse) go to the registers directly to the 19 pins? Are there any problems that the circuit for generating all signals for DSD (reclocking DSD clk, DSD L / DSD R and invert signals) are located at a distance on another board, does not the meaning of reclocking be lost? I am planning to put one 1G125 on the DSD ckl line, I think it will be enough. Thank
Click to expand...

Sorry,
missed your message 🙁

the st!ck's was not meant to be operated As-is.
they require a fifo that isolate and re-clock the input source.
Furthermore i am fonded that the signal split(inversion) must be done before the fifo, and not after.

DSD-Clk pass trough the fifo, dsd1 and dsd2 are copy-and-inverted BEFORE the fifo,
so from the fifo output you gets 5 signal re-clocked and coherent to themselves.
from there, a carefully tuned transmission lines carry the signlas to the sticks left and right.

on the stick's, as soon the clock enter get a buffer that accomplish two things:
1- gurantee that clk can drive all of the 8 clk-in ports of the 575's with enough "power".
2- add a little delay in order to meet the setup time for the 575's

I am NOT an expert by far on this type of designs, but afaik, length has nothing with jitter performances, but rather must be kept in mind from a signal integrity point of view.
A carefully planned tracks and impedance matching is mandatory.

But, again, i am not an expert.
nonetheless the fifo+stick's sound awesome on my system so something good must happen there.

I had a dsc 2.6.2 and a DSC2 but nothing compares to the sticks.
don't get me wrong, everything that pavel did sounded amazing, but i think my rendition adds a little "percentage" more on the goodness scale 🙂

Needless to say that what i did was impossibile without the paving work that pavel a jussi did of that matter.
 
#1,945
gionag said:
Sorry,
missed your message 🙁

the st!ck's was not meant to be operated As-is.
they require a fifo that isolate and re-clock the input source.
Furthermore i am fonded that the signal split(inversion) must be done before the fifo, and not after.

DSD-Clk pass trough the fifo, dsd1 and dsd2 are copy-and-inverted BEFORE the fifo,
so from the fifo output you gets 5 signal re-clocked and coherent to themselves.
from there, a carefully tuned transmission lines carry the signlas to the sticks left and right.

on the stick's, as soon the clock enter get a buffer that accomplish two things:
1- gurantee that clk can drive all of the 8 clk-in ports of the 575's with enough "power".
2- add a little delay in order to meet the setup time for the 575's

I am NOT an expert by far on this type of designs, but afaik, length has nothing with jitter performances, but rather must be kept in mind from a signal integrity point of view.
A carefully planned tracks and impedance matching is mandatory.

But, again, i am not an expert.
nonetheless the fifo+stick's sound awesome on my system so something good must happen there.

I had a dsc 2.6.2 and a DSC2 but nothing compares to the sticks.
don't get me wrong, everything that pavel did sounded amazing, but i think my rendition adds a little "percentage" more on the goodness scale 🙂

Needless to say that what i did was impossibile without the paving work that pavel a jussi did of that matter.
Click to expand...

Thank. Could you lay out the power circuit with all the changes in the ratings of the parts and the transfer to SMD. Тhank
 
#1,950
In the latest update for the Pure firmware I added the ability to connect old multibit DACs.
DATA0 - 30(P9)
DATA1 - 41(P9)
 

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#1,954
Hi guys , I have one of the Chinese DSC1 boards which overall I really like . I am using the upgraded 10k-10k recommended transformers but the sound can be rather lean at times. I did some research and found the suggestion the changing the value of the small ,red ,Wima caps just before the transformers can modify the tone.
Currently the value of the caps is 100/100 which I take to mean 100 nanofarads at 100v.
I did read in the Star dac thread that a warmer sound can be obtained by changing the value to 10-15nf. Would some kind person confirm the validity of this approach and or suggest a cap value to use as a substitue to give the sound more body. Thanks in advance, Gordon
 
#1,955
The value of theese coupling C is determined by the value of load. Pure R or reactive Z.
C and Load creating a filter. That filter acting as low end cut. IN other words, when decreasing the C value You cut out more bass. AND have more phase shifting in low end.
.
So maybe the best way to simple measure bandwidth vith present C value and with replaced value?
.
Maybe this value should be even higher like 1uF...
.
for -0.25db@20Hz standard LF bandwitdh point is -3db@1.6Hz cca.
from that, with standard values:
Co Load
10uF 10K
4.7uF 22K
2.2uF 47K
1uF 100K
0.47uF 220K
0.22uF 470K
0.1uF 1meg
0.01uF 10meg
.
Again, measurements will be useful to You 🙂
cheers
 
#1,960
Perhaps we need a separate thread for Pavel's Pure software but as this is the place it's referenced I'll post here. It's not a DSC2 context but my Buffalo 3SE DAC, which has been operating as an HQP NAA appliance using a Beaglebone Black and an Acko SO3 isolator reclocker. I want to repurpose the DAC in a UPnP use case (so others in the household can use it easily without being exposed to HQP). I've installed the latest version of the Pure software on the Beaglebone and selected the mpd option for UPnP - it works except that the playback is at half speed. I should add that the Acko SO3 is equipped with 90MHz family NDK oscillators.

Ideas?
 
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