Yes. Please do your own simulations. I just did some quick changes to an existing circuit I had on file just to see what could be done.
So, yes, the inductance of the choke directly affects where the low-end rolls off.
- Increasing the capacity of the output cap from 1mF to 10mF actually gives earlier roll-off in the lows.
- Increasing the inductor to 2H starts giving a hump at the low end, but raising the output cap from 1mF to 3mF removes that hump again, flattening it out.
I've never used LTSpice, so I might be missing some real-world info for the caps. Trying to see if I can do static measurement of V/A at certain points to check the bias. Right now Ids is directly tied to the value of the source resistor; changing the supply voltage Ud from 40V to 200V has no effect.
- Increasing the capacity of the output cap from 1mF to 10mF actually gives earlier roll-off in the lows.
- Increasing the inductor to 2H starts giving a hump at the low end, but raising the output cap from 1mF to 3mF removes that hump again, flattening it out.
I've never used LTSpice, so I might be missing some real-world info for the caps. Trying to see if I can do static measurement of V/A at certain points to check the bias. Right now Ids is directly tied to the value of the source resistor; changing the supply voltage Ud from 40V to 200V has no effect.
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@VT-52 How much current are you drawing through the JFET? Maybe DC coupling would be feasible, using the positive rail as speaker ground? My guess is the DC voltage across the inductor may be a bit high, but the DC leakage from the decoupling capacitor could also be significant, so neither solution is perfect.
An RRIO op-amp could be used as a DC servo.
An RRIO op-amp could be used as a DC servo.
With 12R is it around 0.78A. The inductor used here has Rdc of 11 ohms, so it drops around 8.5V. I can raise the supply to whatever value to compensate, so not a big deal.
The other thing that requires attention is the saturation current of the loading inductor. Silicon steel has a very square hysteresis loop, so when you reach the saturation current of the inductor, the inductance will go away all at once. So, you will need to ascertain the current where the inductor saturates.
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Yes I noticed it is at max already, but for now I am just trying to see how this will all behave on paper. I've not input the cap resistances etc either yet. Still fighting LTspice trying to find how to analyze things.
I'm just surprised how much this works like a tube amp up to now. I just don't have an idea yet on how the currents/bias all behave on a FET and I would have thought the ds current was related to the supply voltage (like with tubes).
I'm just surprised how much this works like a tube amp up to now. I just don't have an idea yet on how the currents/bias all behave on a FET and I would have thought the ds current was related to the supply voltage (like with tubes).
A JFET will act like a pentode in terms of V-I characteristics, except it will have Miller capacitance, unlike a pentode.
But one can do two things at once: kill Miller and drive the UJ3 power-jFET;
- buy driving the jFet with a P-MOS, that biases the source/source at 7-8V for instance. . .
That famous amp, a beast with a thousands Dings tells me: why not use a parallel array of twenty or even 50 J175 for this task . . . 😎
That takes out the Sound Destroyer of R12 too
- buy driving the jFet with a P-MOS, that biases the source/source at 7-8V for instance. . .
That famous amp, a beast with a thousands Dings tells me: why not use a parallel array of twenty or even 50 J175 for this task . . . 😎
That takes out the Sound Destroyer of R12 too