Uses LSK189 for input.
Buy at mouser.com: https://www2.mouser.com/ProductDetail/Linear-Integrated-Systems/LSK189-TO-92-3L-BK?qs=T%2BzbugeAwjjUrS49wFak%2Bw==
Uses ECX10N20 and ECX10P20 for output.
Buy for example at: https://gb.profusion.uk/uk/audio/transist/lateral-mosfets
The input JFET pair can be other JFET, too.
Bias in output is set to 300mA.
THD is 0.00020% with the LSK189.
Buy at mouser.com: https://www2.mouser.com/ProductDetail/Linear-Integrated-Systems/LSK189-TO-92-3L-BK?qs=T%2BzbugeAwjjUrS49wFak%2Bw==
Uses ECX10N20 and ECX10P20 for output.
Buy for example at: https://gb.profusion.uk/uk/audio/transist/lateral-mosfets
The input JFET pair can be other JFET, too.
Bias in output is set to 300mA.
THD is 0.00020% with the LSK189.
Last edited:
3 differential stages, may be too much for my tast.
LSK189 can withstand 60V on paper. Did anyone tried it on 100W amplifier, as the input stage? Sometimes, transistors behave weird around their limits.
LSK189 can withstand 60V on paper. Did anyone tried it on 100W amplifier, as the input stage? Sometimes, transistors behave weird around their limits.
Loopgain analysis, phase margin and gain margin should be posted.
What's the deal with the unequal gate stoppers?
>tcd1963
1) Exicons have Zeners built in. No need for gate protection Zeners here.
There were several discussions about this here on DIY, and it was confirmed several times already.
2) The role of caps on GS is to equalize input capacitance on both devices (P and N).
Usually N device has lower capacitance than P device, so some designers ADD extra cap on N device to make them equal.
Example: Rod Elliot's P101.
If capacitances are not equal - that may cause oscillations.
Another way of dealing with this issue, is by using DIFFERENT gate stoppers, using formula RC = constant, where R is...
1) Exicons have Zeners built in. No need for gate protection Zeners here.
There were several discussions about this here on DIY, and it was confirmed several times already.
2) The role of caps on GS is to equalize input capacitance on both devices (P and N).
Usually N device has lower capacitance than P device, so some designers ADD extra cap on N device to make them equal.
Example: Rod Elliot's P101.
If capacitances are not equal - that may cause oscillations.
Another way of dealing with this issue, is by using DIFFERENT gate stoppers, using formula RC = constant, where R is...
Most popular hexfets (IRFP240/IRFP9240) have very similar Ciss, so there is no need for different gate stoppers.
With some other fets that might be not the case...
E.g. Onsemi FQA N/P fets differ more.
With some other fets that might be not the case...
E.g. Onsemi FQA N/P fets differ more.
I guess that's why all the IRFP(9)240-based builds I have filling various rooms with music haven't blown up yet. 😀 So I wasn't completely wrong in my initial statement, since the difference in capacitance is negligible if you stick to "bog standard" FETs. Still learning all the finer nuances of component selection...
I have updated the schematic.
Current is now 1.44mA in JFET pair.
THD is a tiny bit better: 0.00020%
Current is now 1.44mA in JFET pair.
THD is a tiny bit better: 0.00020%
Is it stable? You have a differential input stage loaded with a current mirror which is driving another differential stage which is driving yet another differential stage with a current mirror load.
I can only echo Rod Elliott’s words: “I suspect that it could be a cow to stabilise in a real amplifier circuit”
I can only echo Rod Elliott’s words: “I suspect that it could be a cow to stabilise in a real amplifier circuit”
I have some comments on the schematic
In the simulation what level and frequency is the THD figure for?
My guess is that with 3 differential amplifier stages and an output stage loop stability might be problematic. So I agree with the previous post by PMA.
Also simulation can only take the design so far. The currents in the first and second differential amplifiers are identical which seems unrealistic. I guess it's assuming identical transistors which is only an approximation to real behaviour. It might worth adding some offsets and modifying some of the transistor models to see the effect.
In the simulation what level and frequency is the THD figure for?
My guess is that with 3 differential amplifier stages and an output stage loop stability might be problematic. So I agree with the previous post by PMA.
Also simulation can only take the design so far. The currents in the first and second differential amplifiers are identical which seems unrealistic. I guess it's assuming identical transistors which is only an approximation to real behaviour. It might worth adding some offsets and modifying some of the transistor models to see the effect.
Multisim is not very reliable in detecting amplifier instability. That's what I got for your scheme. Of course, it can be argued that there are different models. If you place the diagram in Multisim format, then I will extract the netlist and calculate the diagram in Qspice with your models. I can calculate the loop gain in the high-signal mode in Qspice.
Attachments
The number of stages worries me. Stability will be a problem. What are the gain and phase margins? I once worked on amplifiers for a company called ILP in the UK. Three stages were essential in order to achieve low harmonic distortion figures for 1kHz, full power output. The quiescent current had to be zero or very close to it as there were no means to adjust it. At low volume you could hear the crossover distortion. I never heard one complaint. I'm of the opinion, though, that stabilty margin is important in listening tests.
Yes. From practical point of view, this topology is close to useless. I hope that the beginners do not try to learn from lineup’s “designs”.
- Home
- Amplifiers
- Solid State
- Rollover - A Decent Amplifier with JFET in and MOSFET out