Occurred to me as well that marginal timing could be having some subtle effect on the sound of DSD512 from PCM. Should find out in a couple of weeks or so. My feeling though is it kind of sounds like it could be something else. Perhaps the FPGA output is subtly different in DSD resampling mode which reduces reclocker timing margin in that one mode? Maybe there is a little more jitter, and or maybe some other slight timing bias.
Also, its not that I don't like the sound exactly. Its not unpleasant, its just that its not exceptional enough to justify $1,400 worth of clocks. All the details of instruments, voices, and sound stage need to come through. As is, some information is getting lost and or masked. IME some dac filters can affect the sound in various ways, some of which can cause inaccurate sounding reproduction. Usually the linear phase option sounds best to me. Could be something ese though. Some people have found signal processing bit depth can have some effect which can be seen in the digital domain prior to conversion to analog (and which can turn out to be audible, something unexpectedly observed with VST plugin filters a long time ago). Also, some of the music we are playing is hi res to begin with. May only matter with very long filters though.
Anyway, we'll see how things are going after the reclocker timing problem is fixed.
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The latest schematic is actually attached to post #1931, but the clock doubler has not changed. The only changes compared to post #241 are four increased resistors to solve a hold time issue.
Link to post #1931: https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7483396
You have extra pins on the fpga, right? Why don't you do a reclock on it directly? The gates have some propagation delay, so you also have to take into account the propagation delay of the buffer... etc, why don't you simply do a reclock from the fpga? 0.8ns io timing on fpga vs ~10ns gate+bufer is ten time better.
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With my configuration file and presumably also with PJotr25's, the output signals from the FPGA are internally (re-)clocked with the master clock.
Of course the FPGA will have all sorts of crosstalk issues you don't have when you reclock the bit clock with a separate flip-flop running off a clean supply, namely package, substrate and common supply impedance coupling from all the digital signal processing blocks in the same FPGA. I try to reset or disable as much of those as possible in the transparent mode (that is, with DSD input while dsdviasd = 0).
Of course the FPGA will have all sorts of crosstalk issues you don't have when you reclock the bit clock with a separate flip-flop running off a clean supply, namely package, substrate and common supply impedance coupling from all the digital signal processing blocks in the same FPGA. I try to reset or disable as much of those as possible in the transparent mode (that is, with DSD input while dsdviasd = 0).
Add some RC on IO output pin to supress those crosstalk? E.g. 10 ohm + 10pF. How crosstalk look on your osciloscope, how your io output pins look on osciloscope?
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You can't see it on an oscilloscope, just like you can't measure HD with an oscilloscope unless maybe it is quite bad (although some expensive scopes have may optional jitter measurement packages, but not that good for audio dac clock frequency offsets).
Adding an RC won't fix the problem and may cause a new time-delay problem.
Really. Don't they teach you this stuff in school?
EDIT: What if I said I have a black box which adds a 100us propagation delay, yet its RMS output jitter is around 10ps. Its possible to do. That's because the two numbers represent entirely different properties.
Adding an RC won't fix the problem and may cause a new time-delay problem.
Really. Don't they teach you this stuff in school?
EDIT: What if I said I have a black box which adds a 100us propagation delay, yet its RMS output jitter is around 10ps. Its possible to do. That's because the two numbers represent entirely different properties.
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600us delay with rc is even 6 times lower than 3.5ns flip flop. and probably better square while rc than flip flop without it.
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That flip flop output risetime might be .5ns. What is a 600us RC going to do to a square wave with .5ns risetime?
What if I said I have a black box with a propagation delay of one year, yet an RMS jitter of 100ps? Do you think the jitter has to be around one year?
What if I said I have a black box with a propagation delay of one year, yet an RMS jitter of 100ps? Do you think the jitter has to be around one year?
Thanks again. I saw that schematic but didn't know that U28 (HC86) can x2 Clock with just R(470R) and C (22pF) at input. Are R and C low pass filter or delay time!? Does the accuracy of R and C values matter and affect the accuracy of the output!?
The EXOR is a 74LVC2G86, actually. The 470 ohm and 22 pF are used as a simple delay circuit. After every transition of the input clock signal, the inputs of the EXOR temporarily have different logic levels on them.
After a rising edge, one input immediately goes high, while the other stays low for a time that depends on RC and then also goes high. The output produces a pulse during the time that the input levels are different.
After a falling edge, one input immediately goes low, while the other stays high for a time that depends on RC and then also goes low. The output produces a pulse during the time that the input levels are different.
The resulting output pulses are about 8 ns wide. The rising edges of the output pulses, which clock the flip-flops and shift registers, are only affected by the delay of the 74LVC2G86, not of the RC circuit. This means that any extra jitter caused by the RC circuit only affects the falling output edges, which are less critical than the rising ones.
If the input duty cycle isn't exactly 50 %, the distances between the output pulses will not be equal. For example, at 60 % input duty cycle, the distance between the output pulses will be 60 % of an input clock cycle, then 40 % of an input clock cycle, then 60 % of an input clock cycle, then 40 % of an input clock cycle and so on. It looks bad on an oscilloscope, but it actually doesn't affect the performance of the DAC.
After a rising edge, one input immediately goes high, while the other stays low for a time that depends on RC and then also goes high. The output produces a pulse during the time that the input levels are different.
After a falling edge, one input immediately goes low, while the other stays high for a time that depends on RC and then also goes low. The output produces a pulse during the time that the input levels are different.
The resulting output pulses are about 8 ns wide. The rising edges of the output pulses, which clock the flip-flops and shift registers, are only affected by the delay of the 74LVC2G86, not of the RC circuit. This means that any extra jitter caused by the RC circuit only affects the falling output edges, which are less critical than the rising ones.
If the input duty cycle isn't exactly 50 %, the distances between the output pulses will not be equal. For example, at 60 % input duty cycle, the distance between the output pulses will be 60 % of an input clock cycle, then 40 % of an input clock cycle, then 60 % of an input clock cycle, then 40 % of an input clock cycle and so on. It looks bad on an oscilloscope, but it actually doesn't affect the performance of the DAC.
Eventually, I got couple of samples of Si3808 VCXOs (for 1024x clock), and implemented simple straightforward DSD256-RZ modulator in XC6SLX9 FPGA. Output was 16-tap differential FIRDAC with 10k resistors. (Bourns 4x10k 1206 0.1% r-networks).
It seems, that advanced Sigma-Delta tricks were useless for improving THD.
My DAC has 119dBFS(A), 19.5bit ENOB and 0.000007% THD, if you trust in REW 5.31.3 calculations.
When I used Cosmos ADC+APU with notch it showed 17.5 ENOB, but 19.5bits ENOB without APU. Is there a REW bug? Do you have any idea?
THD peaks were verified by adding -140dB tone at 3.5kHz (not shown at final measurement below).
It seems, that advanced Sigma-Delta tricks were useless for improving THD.
My DAC has 119dBFS(A), 19.5bit ENOB and 0.000007% THD, if you trust in REW 5.31.3 calculations.
When I used Cosmos ADC+APU with notch it showed 17.5 ENOB, but 19.5bits ENOB without APU. Is there a REW bug? Do you have any idea?
THD peaks were verified by adding -140dB tone at 3.5kHz (not shown at final measurement below).
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What about noise skirts in a busy multitone test, etc.? Isn't this more than a weakly non-LTI system?
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Hi Marcel,
I have no idea why, but I haven't noticed any idle tones at any level from 0 to -60dB, probably because of very high Loop Gain.
I always design it for maximum feedback possible. There is suspicious 3-rd harmonic rise at the level -10dB, but it probably rather related to ESS ADC,
because I noticed the same behavior for several totally different modulator implementations.
Here is a .gif animation of THD at different signal amplitude from:
I have no idea why, but I haven't noticed any idle tones at any level from 0 to -60dB, probably because of very high Loop Gain.
I always design it for maximum feedback possible. There is suspicious 3-rd harmonic rise at the level -10dB, but it probably rather related to ESS ADC,
because I noticed the same behavior for several totally different modulator implementations.
Here is a .gif animation of THD at different signal amplitude from:
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Master clock of my DAC is slowly following input bitrate of the SPDIF signal, so for very long FFTs the frequency usually moves a little bit, causing wide FFT skirts. I doubt that it is important for audio, because of traditional analog sound sources like tape and vinyl have absolutely horrible speed deviations.
What I notice while my best clock is out of commission for awhile and I am using my second best S-cut crystal oscillator, is that that it still sounds pretty good, but the acoustic string bass sound is soft. Its lost its punch, details of the string plucks, and most of the wooden body sound. If the difference is related to something I know is different about the oscillators, it is that the backup oscillator has more 1/f noise at offset frequencies in the audio band where the string bass is now less precisely reproduced. BTW, not just my own opinion. Other people familiar with the system have noticed the change too. Also, IME its not at all the same type of sound effect produced by professional tape machines. It still sounds like a string bass on tape, even if its distorted in other ways than what some dacs can do.
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OK, but any normal sigma-delta modulator has loads of loop gain in the band of interest and almost none far outside the band of interest...
What does the digital spectrum around half the sigma-delta sample rate fs/2 look like?
I could think of four explanations:
1. You managed to design a DAC with less second-order intermodulation distortion between the idle tones around fs/2 than mine.
2. You use a particularly effective dithering scheme to spread out the idle tones around fs/2.
3. You use a particularly effective chaos scheme to reduce idle tones around fs/2. Lars Risbo published one in his PhD thesis, although it has other disadvantages - noise modulation when the DAC settles imperfectly. (He adds an all-pass around fs/2 to the noise transfer function, which translates to an unstable resonator at fs/2 in the loop filter, which destabilizes the idle tones.)
4. You intentionally or unintentionally add an offset to move idle tones far enough from fs/2 such that their second-order intermodulation product falls outside the audio band. That's the oldest trick in the book, but not a very good one, as a signal that is approximately opposite to the offset moves the intermodulation product back into the audio band again.
Regarding 1, we managed to find out that the -130 dBFS low-level distortion products (at -60 dBFS, 1 kHz input level) of the DAC of this thread are due to second-order intermodulation between
idle tones around fs/2. At first, it seemed to be dominated by the output filter, but that later turned out not to be true. Other suspects are data-to-reference or data-to-clock crosstalk. Details are in the attachment of post #3265, https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7686002 (The DSC 2.5.2 has similar distortion products that are about 20 dB stronger, but it is NRZ.)
With properly dithered quasi-multibit sigma-delta modulators, there are no such idle tones, so they can't intermodulate either - but you pay with less effective noise shaping.
In any case, it's completely up to you, but if you are prepared to share more information about your design, please do.
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