We are in LaLa Land.
If we are in LaLa land, there is no difference whatsoever between NRZ, RTZ and RTZ(I), except signal levels and as in LaLa Land there is no noise or distortion whatsoever in electronic circuits we have perfect sound forever and everything sound the same.
Oh, this is of course also true in SIM land, UNLESS we make sure to make the SIM sufficiently complex, at which point is is still faster to make a PCB, fab the bl00dy thing and measure it.
All the points of debate, contention etc. are about the way REAL circuits behave, IN THE REAL WORLD and strategies to mitigate the problems the real world causes.
Let me first state what we deal with here is pretty low down in levels on the FFT, at a point where we might suggest it is not audible IN ITSELF.
Second, audibility, presume we are listening with an open mind in the first place, is subtle.
It mean if you took my main system and played two variants with those subtle differences to "Otto Normalverbraucher" (german for Joe Bloggs) used to listening to a TV sound bar (or just TV sound), an Amazon Echo or Apple Homepod or maybe a B*se waveradio and fake 10 USD BT earbuds that copy apple, they will hear absolutely no difference, will note "maybe it sounds a bit better than my .... (insert specific plastic box the size of a beer can) and "You sure have wicked bass" (Dual 12"Active subs in a small room).
In technical terms we are dealing with intermodulation.
While semiconductors have gotten better (really? Where are superior replacements for 2SB737, 2SK146 and 2SJ73 and improved lateral FET's?) and have less issues at RF, in typical loop feedback based circuits distortion rise reaches a quite steep slope with frequency long before we get into the MHz region.
This means quite low levels of RF residuals that leak into audio circuitry can have an outsized (well, not really, just on casual thinking) effect.
Seeing bohrok's Sim's my thought about common mode problems might be bogus, es it shows differential mode ones.
Thor
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For an analogue designer, the main problem with modern CMOS processes, or at least with their core transistors, is the very poor voltage handling and the resulting low supply voltages. I haven't done much in 90 nm, but I guess the normal core supply is at most 1.5 V. Besides, small transistors match poorly and have lots of 1/f-noise. Fortunately, there are also I/O transistors that can handle a bit more, like 3.3 V.
Making really low noise current sources gets difficult when the supply voltage is low, but you could also think of a resistor string DAC: string of equal resistors with switches on the taps. The routing can be kept manageable with row and column decoders, I hope. The output impedance is code-dependent, which causes distortion. An on-chip buffer could hopefully keep that under control (although designing that buffer is also not trivial at low supply voltages).
Well I'd take it on the chin Mark, I can't contribute with measurements so I appreciate to see measurements from those that can. I will try things though and post what I hear or can't hear , obviously not helpful to everybody but maybe to some . It could be the type of resistors or maybe because they are more closely matched ? either way I think it was worth doing
The resistor thing seems have to do with Excess Noise, which is mostly current noise. Some resistors optimized for audio are especially low noise while giving up some ground on other attributes.
Excess noise results in spectral line noise skirts that can be seen on a hi-res FFT (one of the good and useful things Bohrok2610 deserves credit for demonstrating).
The noise skirts are also from clock close-in phase noise.
Interestingly, to me and on my system resistor excess noise and clock close-in phase noise have some similarities. Both produce a kind of what I call a "blur" to the sound, which tends to mask lower level details. Close-in phase noise also seems to affect precision of imaging, but haven't noticed that for resistor excess noise.
Excess noise results in spectral line noise skirts that can be seen on a hi-res FFT (one of the good and useful things Bohrok2610 deserves credit for demonstrating).
The noise skirts are also from clock close-in phase noise.
Interestingly, to me and on my system resistor excess noise and clock close-in phase noise have some similarities. Both produce a kind of what I call a "blur" to the sound, which tends to mask lower level details. Close-in phase noise also seems to affect precision of imaging, but haven't noticed that for resistor excess noise.
1.8V But yes.
4 X 64k Transistors is still chump change in 2024.
True, but 64k in parallel mitigate that after all...
What I was really commenting on was that at one point we had dynamic element matching and other interesting stuff in a bipolar ECL Chip (TDA1541) with 2^16 real discrete output states at 192khz sample rate. It still sounds good (I dislike perfect) 35 or so years later. Then Came 18 Bit, 20 Bit, even 24 Bit (bit dodgy that on one a multibit DAC with 118dB SNR)
Then came pure 1 Bit (thank you Cirrus Logic and Philips) which did away with all that complex analogue precision. Prices per die dropped to next to zero and the new 1 Bit chips could be sold even more expensive. Accounting loved it.
Eventually someone figured out it didn't sound all that great and we are back at adding more and more "bit's" with much more complex digital processing.
Soon we may finally again see a DAC Chip that can go up against TDA1541 with more of a chance than a snowball in the centre of sun and may be beat it. Or it will not happen, why dent profits as we are now in LaLa Land, where everything is perfect and sounds the same anyway.
Thor
Only other time I really messed with resistors was for I/V in TDA1541A dac , I've tried many there and liked the TX2575 best, luckily it only needed a pair
Just an interesting article:
http://fpga.cool.coocan.jp/wordpress/?p=1744
There are objective differences feeding the FIR (NRZ) DAC with different CPLD / FPGA's but otherwise the same.
Thor
http://fpga.cool.coocan.jp/wordpress/?p=1744
There are objective differences feeding the FIR (NRZ) DAC with different CPLD / FPGA's but otherwise the same.
Thor
That's something John Westlake talked about years ago. He talked about jitter as function of the how FPGA resources are located on the chip and how they are routed around including to output pins. In addition, its clear such chips can radiate EMI/RFI, etc.
Turns out this is something Andrea Mori addresses in his dacs, and that I believe may receive further attention as newer boards are developed. Its one reason my experimental dac is divided into separate shielding and isolation domains.
Turns out this is something Andrea Mori addresses in his dacs, and that I believe may receive further attention as newer boards are developed. Its one reason my experimental dac is divided into separate shielding and isolation domains.
IMO it’s wrong to compare PCM to DSD.
When converting PCM into DSD, the real benefit is the 1 bit D/A converter instead of a multibit Converter.
So you should compare 1bit to multibit D/A converters, It doesn’t matter what source file you start with, PCM or DSD.
Hans
Hans,
There can be practical differences depending on source format. It easier to turn 16/44 or other PCM into good sounding DSD, as opposed to the other way around.
Our usual rule is that if its PCM <=24/192 then convert to DSD256, but if its, say, DSD64 then just play it as it is. In the end it usually sounds better that way.
Moreover, it matters what algorithm is used to convert PCM to DSD, as they all sound different. Often even a bigger issue going from DSD to PCM.
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If anyone has one of Marcel's RTZ dacs and would like to try it with I2SoverUSB, and all that's standing in the way is how to patch I2SoverUSB into the Amanero format pinout on Marcel's dac, I have a few boards that were designed for something else, but can work to connect an I2SoverUSB to Marcel's dac. The board can be seen in use in the pics at:
https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7417213
https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7417255
Its the small green board in the bottom of the stack. PM if interested.
https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7417213
https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7417255
Its the small green board in the bottom of the stack. PM if interested.
Designing a discrete DAC with an FPGA poses a significant challenge, particularly when aiming for an SNR of around 120dB. Manual configuration of IO placement becomes crucial. In the case of Spartan6, the choice of bank also matters since there are banks with higher and lower SNR. Therefore, using older software like ISE 14.7 is necessary, as manual placement might not be possible in newer tools like Vivado. Further improvement can be achieved by splitting the design into two FPGAs: one for the digital section, DSM or oversampling, and the other for the analog, shift registers, and IO.
You claimed that there is significant common noise in Marcel's design (due to lack of interleaving) and presented your mitigation strategy. My simulations show that the interleaving works as designed. Load after shift registers has nothing to do with interleaving as such. Whether or not there is common or differential noise in Marcel's design is another question and I was not trying to prove anything related to that.
I have no reason to defend Marcel. I just posted the simulations since some of your claims about the design were not correct.
Since this discussion seems to veer towards other things than Marcel's RTZ dac maybe we should also discuss this:
https://www.audiosciencereview.com/forum/index.php?threads/1-bit-dac-launched-by-topping.52865/
https://www.audiosciencereview.com/forum/index.php?threads/1-bit-dac-launched-by-topping.52865/
I think Ed Meitner was the pioneer. He called this "LIM" Logic Induced Modulation. These days we understand this comprises a range of phenomena, all of which are down to the use of (C)MOS. In an SMPS with Mosfets or a class D Amplifier we "see" those problems, but in logic IC's, never mind VLSI Logic, they are occulted.
With TTL we have big load steps between L & H but LIM is minima due to the way the logic thresholds work.
With ECL we are dealing with differential circuits on CCS tails operated outside saturation, hence no LIM.
With CMOS? Well.... Glad you asked, you will not be.
https://www.digikey.fr/htmldatasheets/production/1428461/0/0/1/74HC-T-U-User-Guide.pdf
In this link a bit of information. On page 25:
We don't see "unit load" in the datasheet any longer.
What you see here is what happens in the "crossover region" between L & H where both Mosfet's conduct a little.
The static current of CMOS is close to zero, but a single gate will have a short "blip" of fractions of a mA whenever it transition L to H or H to L.
This current is ALWAYS common mode, even a carefully "balanced" arrangement will not cancel these.
What does this current do? Cause power consumption that rises with clock frequency. Anything else?
Well, our real parts have inductance, resistance and capacitance in the lead-frame, bond-wire and PCB. The current spikes are very high delta I / delta T, so a current flowing here will cause a voltage that different from GND or Vcc. This voltage is high delta V / delta T and appears across what is in effect an LC tank.
On an immediate point, as switching points are defined by Mosfet Threshold voltages referenced to GND and Vcc, if there is any shift, the switching point is shifted.
This is usually called ground bounce, but also affects Vcc.
Now imagine we have many gates each made up from multiple inverter circuits, all switching as a result of a single clock edge, but because we have cascaded circuit with non-zero delay, there is a round of switching "blips" rippling through the IC internally. lucky, internally on chip we have a consistent reference, or we have real issues.
But for external signals entering the IC pin's the only time when we get consistent timing free from bounce is if the IC internally has reached "steady state" before the next edge AND the LC Tank circuits have stopped ringing.
Using multiple solid ground planes, via stitching and careful layout we can reduce the effects in our PCB pretty well. Inside the IC Lead frame? Less so. We have no control, except picking the IC.
The physically smaller an IC, the shorter the path between actual Chip and PCB. So all else the physically smaller IC package is better. Leadless IC's are better.
IC's with a standard 74 series pin outs are terrible, the distance between Vcc and GND pin is the longest distance possible and there is only one pin each.
But we have another problem. Mosfet's have gate capacitances that must be charged/discharged. We see typically 4pF as input capacitance per IC pin for HCMOS, we can just calculate for that and we are good, right?
Right.
Of course not. Capacitance is signal dependent.
So as we see gates and inverters switching, the current needed to charge these capacitance's depends how close we are to the switching point.
And where does this current flow from/to? Ground/Supply. Now it may be clearer why a full ground and supply plane is recommended for all IC's in the power supply and signal domain and why "decoupling" individual CMOS IC using Ferrite Beads or Inductors is COUNTERPRODUCTIVE in this application.
All in all something as simple as a single digital gate raises considerable complexity in the real world.
The key is to use the most simple internal structure IC's as actual Bit switches, with good layout and make sure their ground bounce is settled before the clock edge arrives that controls the output timing.
The rest just needs to be functional and in the same clock domain, with a layout that avoids noise from the "dirty" logic entering the ground/supply for the Bit switches.
Isolators have their own challenges and are not always necessary.
Mind you, I have used galvanic isolators myself.
Thor
No, we can ideally have 105dB peak playback (THX reference level) in a room with < 20dB backround noise, I would suggest that around 115dB suffice to be reliably inaudible.
However SNR usually is averaged, not peak and bandwidth limited.
Apples and Oranges even more than DSD vs PCM.
Thor
The required SNR greatly depends on the music being listened to and the environment. Playback at -60dBFS is essential for classical music, effectively eliminating 10 bits. Furthermore, the output level is significantly reduced in multi-system setups where high-efficiency horn drivers are used. Based on my experience, an SNR of around 110dB is considered the minimum requirement in such environments. Hence, I've set the target at 120dB.
Indeed, in environments like those of records, where the SNR is around 60dB, aiming for an SNR of 110dB may seem excessive. However, it's important to note that SNR represents the ratio of signal-to-noise levels, and at 0dB, they are equal. Yet, 0dB is not the threshold at which sounds become inaudible to the human ear. The SNR may be negative in noisy urban environments, with noise levels surpassing the signal, yet people can still communicate with each other. It seems there's a qualitative aspect to noise, where some are more intrusive than others. If the noise isn't intrusive, even a negative SNR might not pose much of an issue, as is often the case with records. However, in the case of DACs, noise becomes more intrusive, so having seemingly unnecessary figures might be favorable.
Since this is a diy-site FPGAs are challenging just for the packaging alone. Most FPGAs are only available in BGA which is more or less impossible for most diyers. Suitability for diy by avoiding FPGAs is one of the key features of Marcel's RTZ dac.
I changed the resistors of second stage (OPA1678) to have same gain as your original filter. Distortion at 10kHz improved only marginally (about 0.3dB). Sorry, no more measurements from me on this thread so you will just have to take my word on this
EDIT: Since level was now 6dB lower the marginal improvement may be due to just having lower distortion in ADC.
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