Changing J2 IDSS (which is 2SK117GR or 2SK880GR (SMD) having the right Vgs (off) range, good noise spec, right Yfs for this circuit), won't be a productive way for drastically changing the Vf apart from targeting small adjustments. Their IDSS range within GR is limited for affecting Leds Vf strongly. Best practice is to forecast well the type and number of Leds by using the test jig I have shown which takes into account the current provided by the J2 sample to be used. Adding a resistor is a valid Vref boost solution and there are pads accepting it but its contribution better be as minimal as possible so to keep the Vref lower in impedance. Stays a more "rigid" Vref that way.
Hi Salas,
I recently bought dam board. Its powering is: +5V/250mA for digital and +/-5V/20mA for analog (resistor ladder). Max is 5.5V for both cases which means I could also try SSLV for analog part. With this I have following considarations:
1. What is better theoretically for powering -/+5-5.5V/20mA resistor ladder in dam board Ref D or SSLV? Is the resistor ladder considered to be digital or real analog part of dac?
I want to compare SSLV and Ref D here. SSLV of course will be mosfet version.
2. My observation is that Vref cap has bigger impact on regulator performance than zobel one. Since it is small load 20mA and no zener diode, could I apply same Vref capacitor rule for Ref D as for SSLV meaning that its value in Ref D could be decreased from 1000uf electrolytic to 10uf MKP?
Thanks,
I recently bought dam board. Its powering is: +5V/250mA for digital and +/-5V/20mA for analog (resistor ladder). Max is 5.5V for both cases which means I could also try SSLV for analog part. With this I have following considarations:
1. What is better theoretically for powering -/+5-5.5V/20mA resistor ladder in dam board Ref D or SSLV? Is the resistor ladder considered to be digital or real analog part of dac?
I want to compare SSLV and Ref D here. SSLV of course will be mosfet version.
2. My observation is that Vref cap has bigger impact on regulator performance than zobel one. Since it is small load 20mA and no zener diode, could I apply same Vref capacitor rule for Ref D as for SSLV meaning that its value in Ref D could be decreased from 1000uf electrolytic to 10uf MKP?
Thanks,
I have only experienced in my system Dim Dim's dam. He has sslv1.1 +/-10V for analog and 5V for digital rail with Reflektor. Why is that when you say max is +/-5.5V for analog too, is it better +/-10V but not permissible any more in newer version boards for the ladders?
I don't have information what is better reg choice for ladders because nobody wrote or brought me over one with stacked Reflektor +/- for the analog to compare. I would theoretically try sslv first. For the philosophical question if a converter section like this is analog or digital, I am not expert but as I am simplistic I would think because Thevelin equivalents apply to analyze R2R it should be analog at heart?
In Reflektor the Vref filter cap is big because digital appreciates very low 1/F noise. That means slower too. On analog maybe I would experiment different in that area. So try compare and let us know. There could be a good enough subjective noise floor threshold in the audio band with more economy on Vref capacitance value for applying to the dam analog stage.
I don't have information what is better reg choice for ladders because nobody wrote or brought me over one with stacked Reflektor +/- for the analog to compare. I would theoretically try sslv first. For the philosophical question if a converter section like this is analog or digital, I am not expert but as I am simplistic I would think because Thevelin equivalents apply to analyze R2R it should be analog at heart?
In Reflektor the Vref filter cap is big because digital appreciates very low 1/F noise. That means slower too. On analog maybe I would experiment different in that area. So try compare and let us know. There could be a good enough subjective noise floor threshold in the audio band with more economy on Vref capacitance value for applying to the dam analog stage.
Thanks Salas/
I saw Dim Dim's build. He has dam1021. I am talking about oem version dam1121.
Max 5.5V means 10% tolerance to 5V (4.5V-5.5V) in this case.
I already use stacked Ref Ds -/+5V for my pcm1704 build and another stacked two running at -/+7V for IV. It sounds fantastic.
As far as dam R2R ladder. I will try and then let you guys know:
-/+5V Stacked Ref Ds vs SSLV for R2R ladder in dam.
And then the same but with MKP instead of electrolyte in Vref.
BTW I already tried SSLV with 100uf! MKP in Vref. The cap is huge (used in my tube buffer as main rectifier). The results are ... interesting
I saw Dim Dim's build. He has dam1021. I am talking about oem version dam1121.
Max 5.5V means 10% tolerance to 5V (4.5V-5.5V) in this case.
I already use stacked Ref Ds -/+5V for my pcm1704 build and another stacked two running at -/+7V for IV. It sounds fantastic.
As far as dam R2R ladder. I will try and then let you guys know:
-/+5V Stacked Ref Ds vs SSLV for R2R ladder in dam.
And then the same but with MKP instead of electrolyte in Vref.
BTW I already tried SSLV with 100uf! MKP in Vref. The cap is huge (used in my tube buffer as main rectifier). The results are ... interesting
Hi Salas,
I plant to power fpga in dam1021 directely @ 1.2V. I do not know how much current it is drawing yet, however if it is below 0,5A then is it possbile to run Reflektor D for this? Just with residual voltage ~1.2V (no leds - all shorted)? What supossed to happend for filtering cap 1000uf in such case?
I plant to power fpga in dam1021 directely @ 1.2V. I do not know how much current it is drawing yet, however if it is below 0,5A then is it possbile to run Reflektor D for this? Just with residual voltage ~1.2V (no leds - all shorted)? What supossed to happend for filtering cap 1000uf in such case?
Unfortunately not again, and I will explain why. There is the M2 Vgs threshold putting a stop. That is why I designed with weird TTL level MOSFET there, to keep it low. On the other hand maybe I can have a look again if we can get away with some BJT that has Vbe instead of Vgs and its 1V or below at such currents. I had looked back then but I don't clearly remember why I skipped it as a build option. Probably the final spec or the phase margin had bugged me. Not even as flexible. J2 option would not find voltage space to work for instance. But if it is for a special occasion, maybe worth revisiting.
Well some good 1.2V powerfull regulator is definately something that is missing in the Salas Regs family. I would use it for FPGA or XMOS cores powering.
Hymn, maybe. I will stick to 1.2V/2A belleson for now. I have one for 3.3V and it is really good. Even better than some shunts!
I revisited my old theoretical try out files and the conclusion was/is when directly modding to 1.2V with output BJT & by simplifying the mirror, those actions also simply kill the spec. It will need be a different enough approach or a more parts involving similar architecture, so leave it as its and use it as pre-reg still good down to about 3V output.
To try a divider and to still keep the Zo decent, the divider's parallel resistor to ground would need a large enough value lytic across it. One good thing with the divider is it will divide the noise too and it can also be located very near to the receiving chip. Two resistors and a compact 6V lytic. Which can double role as the chip's local decoupler.
Its already a chunky value for the CCS range we use and all brands will have a much high ripple current spec in such a component. Well covering and more. So not necessary to make it bigger but you may find that higher capacitance models at the same voltage spec can have better DF and ESR for instance. Or same capacitance models may have better characteristics when having higher voltage spec.