I don't understand the poor PSRR.
The output voltage is defined by the gate voltage not the power rails.
The output voltage is defined by the gate voltage not the power rails.
About early effect , the 2sj164 sim model has 138 ma for 0v gate when drain is 50v while the k has only 1.8ma . Is this normal or wrong modeled?
Surely the output of any FET is defined by gate and drain voltages? FETs are not high output impedance devices like BJTs.nigelwright7557 said:
PS I thought Early effect applies to BJTs alone - it expresses how far short the transistor falls from being a perfect current source.
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Two distinct mechanism play a role here, and they shouldn't be mixed up: one is the equivalent of the Early effect for FET devices, the channel modulation, which happens under all conditions, including DC, and apart from massive feedback or cascoding has no solution, the other is the Miller capacitance effect between D and G, which is frequency-dependent and can easily be cured with a low drive impedance (the cascode also works in this case)
