I'm hoping Harry/Jocko or others might weigh in on the design of a proper divider for digital audio applications. Specifically I'd like a 128Fs MCK at 24.576MHz, a 64Fs BCK, and the Fs LRCK.
My inital thought was a quality 24.576 clock oscillator feeding a CMOS monolithic synchronous counter. The problem is that the propagation delay is nearly 50ns, so I would worry that clock syncronicity is lost.
Second thought is a 49.152MHz clock, and all signals are generated by the counter. Now I have to worry about using a non-fundemental mode oscillator.
Add to this the idea that CMOS logic induces a lot of phase noise. (?) What is the alternative? ECL logic? Analog claims 4ps jitter added by an ECL gate.
I have to wonder at the quality of the dividers in chips like AD1896 compared to a solution that board members here would create.
Any thoughts? What would you use in such a circuit? (Jocko, if you chime in with part suggestions, I'll promise to buy--not sample--them. ^_^)
My inital thought was a quality 24.576 clock oscillator feeding a CMOS monolithic synchronous counter. The problem is that the propagation delay is nearly 50ns, so I would worry that clock syncronicity is lost.
Second thought is a 49.152MHz clock, and all signals are generated by the counter. Now I have to worry about using a non-fundemental mode oscillator.
Add to this the idea that CMOS logic induces a lot of phase noise. (?) What is the alternative? ECL logic? Analog claims 4ps jitter added by an ECL gate.
I have to wonder at the quality of the dividers in chips like AD1896 compared to a solution that board members here would create.
Any thoughts? What would you use in such a circuit? (Jocko, if you chime in with part suggestions, I'll promise to buy--not sample--them. ^_^)