Please, explain why two complimentary input stages.

I would like to ask why very large public address amplifiers often employ two complementary input stages? Using two different sub-circuits for the input necessitates that the two sub-circuits behave exactly in the same way. My impression, which may be wrong and that is why I am asking, is that, making NPN and PNP transistors to match to a very high degree, is expensive and difficult.
 
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The type of input stages I am asking about employs a current source, a differential pair and optionally a current mirror. I am not asking about balanced inputs, which would need an op-amp before the actual power amplifier input.
 
Double input stages like this are typically used to drive a push-pull VAS. Why a push-pull VAS is another question of course!
From different circuits employing such input stages, it is clear the two input stages work in opposition. While the output (transconductance) current increases in one input stage, in the other, it decreases. Therefore, one transistor in the VAS becomes more conducting while the other becomes less conducting. My logic tells me this should increase the voltage gain of VAS compared to having only a current source instead of two transistors working in opposition. The advantage seems to be having a VAS that is actively driven to both rails, instead of relying on a current source to pull the VAS towards its reference rail.
 
You haven't provided an example circuit leading to various interpretations of the question. Current source stages do not have symmetrical slew rates (in general). This affects distortion at HF.

Matching of transistors is not an issue if DC trim or servo is implemented and is also assisted by current mirrors.
 
Competent is an arbitrary judgement. Asymmetry can be seen in many designs and is more manifest into reactive loads. The difference in waveform triangulation can be seen between rising and falling edges as the frequency rises. Even if the measured rise times may be similar, the shape of rising and falling edges differ. A significant number of designs never make to their -3dB bandwidth limit without signal triangulation into reactive loads. Are these designs competent?

Some favor symmetrical topology for this reason.
 
A significant number of designs never make to their -3dB bandwidth limit without signal triangulation into reactive loads.

Slew rate, and triangulation thereof, is not a function of the load at the amplifier's output. The slew rate of an amplifier is a function of the input stage's quiescent current, the second stage's quiescent current, the size of the amplifier's compensation capacitor and the value of the amplifier's internal parasitic capacitance, especially at the output of the second stage.
 
Slew rate, and triangulation thereof, is not a function of the load at the amplifier's output.

Yes it is. As the current draw of the output devices increases, the beta of BJT falls requiring more current from the drivers. Therefore the load has a ripple effect into the earlier stages of the design. Capacitive loads demand a lot of current. A simple simulation in LTspice proves the point. Distortion variance with load also proves the point. If your amplifiers are completely immune from load, that is a good trick.
 
Yes it is. As the current draw of the output devices increases, the beta of BJT falls requiring more current from the drivers. Therefore the load has a ripple effect into the earlier stages of the design. Capacitive loads demand a lot of current. A simple simulation in LTspice proves the point. Distortion variance with load also proves the point. If your amplifiers are completely immune from load, that is a good trick.

Capacitive loads do not necessarily "demand lots of current": the current drawn by a capacitor depends on the signal frequency and the value of the capacitor. In any case, the load at the output of a competently designed amplifier should not have any effect on its slew rate.

Someone once said "The less people know the more stubbornly they know it", an apt aphorism methinks as you seem impervious to the truth. Perhaps some civic-minded person will step in here to enlighten you. Alternatively, you would educate yourself no end by reading a good textbook on elementary linear electronics theory.
 

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edbarx, the reply I initially offered remains valid. The vbe of the input transistors is controlled by the value of the emitter resistor. The matching problem moves to how well the emitter resistors are matched and how accurate the current mirrors perform.

Input offset voltage is cancelled by the opposing base currents of the NPN and PNP devices. If one device's base current is double the other, the input offset voltage is still only the same value, or less, as if one device was used. What also helps is a low input impedance so that differences in base currents have less contribution to the offset voltage, same as for one device.

The current mirrors may need some effort for matching. This is sometimes done by altering the emitter resistors of the NPN and PNP current mirror transistors instead of device matching. Modern complementary devices can have good matching.
Does any of this address your initial question?