Hi Kurt,
I´ll try to improve upon that, maybe I´ve got it right this time.
NPC is well known for very good filters, but not for flagship DACs.
I do know only one CD player featuring NPC DACs and that´s an obsolete Densen player which sounds worse than you think
Nigata is hardly available
The ESS is puzled with at the time being, you can have some additional info in PB if you like.
A very compact layout and paying thorough attention to PSU both digital and analog pays of huge sonic improvements. If you look at our earlier project, you´ll see how far we took it.
Yeah right, lokal bypassing of the digital circuits is very important, but also damping between the circuits is important.
If you look upon the measurements done in DAC distortion, 8416 IMHO has its justification with PDUR 1, but mostly performance degrades from 96-192 KHz in digital circuitry.
Excactly pin 20 to VL.
You are welcome to do so, could be fun actually.
Ciao T
I´ll try to improve upon that, maybe I´ve got it right this time.
NPC is well known for very good filters, but not for flagship DACs.
I do know only one CD player featuring NPC DACs and that´s an obsolete Densen player which sounds worse than you think
Nigata is hardly available
The ESS is puzled with at the time being, you can have some additional info in PB if you like.
A very compact layout and paying thorough attention to PSU both digital and analog pays of huge sonic improvements. If you look at our earlier project, you´ll see how far we took it.
Yeah right, lokal bypassing of the digital circuits is very important, but also damping between the circuits is important.
Yes so it is in theory.
Yes I agree
If PDUR is liftet in hardware mode you only loose 192KHz, since the chip supports up to 105 KHz in PDUR 1.
If you look upon the measurements done in DAC distortion, 8416 IMHO has its justification with PDUR 1, but mostly performance degrades from 96-192 KHz in digital circuitry.
I don´t have AP Two.
Excactly pin 20 to VL.
You are welcome to do so, could be fun actually.
Ciao T
@ ThorstenL:
When can we expect you to upload FPGA-code including SPDIF receiver and state of art PLL circuit??
It could be great in the open source project....
When can we expect you to upload FPGA-code including SPDIF receiver and state of art PLL circuit??
It could be great in the open source project....
Hi,
Actually, I care little if tubes or not, but I am interested in music sounding realistic and tubes more often get this right. But in principle anything goes. For example, I rather like DNM Solid State electronics. What I do not like is the generic, artificial and boring hifi / high end sound that sounds nothing like real music, but totally artificial and processed.
I remain mystified (in my own recent testing that one was at the very bottom of the pile, a big pile too), but there is no arguing taste.
That should help. Consider doing the same with the powersupplies.
And even if you insist using the CS4398, please reconsider the CS8416. It is actually really bad by any fun loving standard.
My personal choice BTW for the kind of DAC you are working on would be an AKM receiver and an AKM DAC, these are generally similar to the CL Stuff (AKM and CL used to co-operate closely, now all the good chip designers work at AKM), but tend to have fewer bugs and perform better.
Also, I would still very, very seriously look at a secondary PLL at least.
Clock jitter minimisation is about halve the rent for any DAC design.
Or alternative have a way to slave the transport to a clock local at the DAC, but then you might as well also use I2S communication and the project goes off the scope.
If an ASRC was absolutely needed I would probably go with the BB SRC Chip (or the NPC one), but make sure it can be disabled (Jumpers?).
Powersuppies, I'd go for something similar to the Teddy Regs, probably using discrete Sziklai transistor pairs for the emitter follower and running a fair bit of extra current (just load the rails with resistors) to bring down the emitter follower output impedance. And I would use what most may find ridiculously big value capacitors on the Base of each of these emitter followers.
Analog Stages discrete and zero feedback I completely agree, make the power supplies for this zero loop feedback as well though, it is audible.
BTW, just for reference. I build a pretty straightforward DAC using CS8412, AD1890 and CS4390 with 317/337 supplies (all basically earlier versions of what you are intending to use) build to "best practice" standards in the mid 90's. Very good Op-Amp output, but not discrete.
I was rather disappointed when the result sounded rather drastically worse than the analog output of my heavily modded Marantz CD-67 (I wrote about the CD-67 Mods in TNT-Audio.com, the CDP still also used Op-Amp's). Of course that modded Marantz Player was rather outstanding and notched up it's own list of "giant slayings".
The experience then set me off onto path rather divergent from the mainstream, though every few years I survey the latest crop of chips and stuff.
And I repeat that I would love to see a really good "community" DAC design that goes beyond the usual stuff in both execution and performance.
Ciao T
Actually, I care little if tubes or not, but I am interested in music sounding realistic and tubes more often get this right. But in principle anything goes. For example, I rather like DNM Solid State electronics. What I do not like is the generic, artificial and boring hifi / high end sound that sounds nothing like real music, but totally artificial and processed.
I remain mystified (in my own recent testing that one was at the very bottom of the pile, a big pile too), but there is no arguing taste.
That should help. Consider doing the same with the powersupplies.
And even if you insist using the CS4398, please reconsider the CS8416. It is actually really bad by any fun loving standard.
My personal choice BTW for the kind of DAC you are working on would be an AKM receiver and an AKM DAC, these are generally similar to the CL Stuff (AKM and CL used to co-operate closely, now all the good chip designers work at AKM), but tend to have fewer bugs and perform better.
Also, I would still very, very seriously look at a secondary PLL at least.
Clock jitter minimisation is about halve the rent for any DAC design.
Or alternative have a way to slave the transport to a clock local at the DAC, but then you might as well also use I2S communication and the project goes off the scope.
If an ASRC was absolutely needed I would probably go with the BB SRC Chip (or the NPC one), but make sure it can be disabled (Jumpers?).
Powersuppies, I'd go for something similar to the Teddy Regs, probably using discrete Sziklai transistor pairs for the emitter follower and running a fair bit of extra current (just load the rails with resistors) to bring down the emitter follower output impedance. And I would use what most may find ridiculously big value capacitors on the Base of each of these emitter followers.
Analog Stages discrete and zero feedback I completely agree, make the power supplies for this zero loop feedback as well though, it is audible.
BTW, just for reference. I build a pretty straightforward DAC using CS8412, AD1890 and CS4390 with 317/337 supplies (all basically earlier versions of what you are intending to use) build to "best practice" standards in the mid 90's. Very good Op-Amp output, but not discrete.
I was rather disappointed when the result sounded rather drastically worse than the analog output of my heavily modded Marantz CD-67 (I wrote about the CD-67 Mods in TNT-Audio.com, the CDP still also used Op-Amp's). Of course that modded Marantz Player was rather outstanding and notched up it's own list of "giant slayings".
The experience then set me off onto path rather divergent from the mainstream, though every few years I survey the latest crop of chips and stuff.
And I repeat that I would love to see a really good "community" DAC design that goes beyond the usual stuff in both execution and performance.
Ciao T
Hi,
Then you might as well use a WM8804 in Hardware mode. It shows so dramatically lower output jitter (tested on AP2) compared to CS, it is not even funny. And yes, it is very audible compared to the CS. I recently had a chance to help a DAC Vendor to re-design his product for the WM instead of CS (all else remained in place) and it has been getting much increased sales and excellent reviews ever since.
The only reason not to use the 8804 is the funky behaviour at 176.4KHz but if you give that up anyway, you might as well use the 8804.
Oh, but make sure to give it a very clean low jitter reference clock. It seriously shows up.
There are other ways (arguably harder) to measure jitter, What AP adds most is a way to generate a precisely defined source jitter pattern which you can easily look for in the FFT of the output, so you can easily how well a receiver suppresses jitter (Hint, in case of the Cirrus Logic products - not all is the answer - hence I refused to make or get involved with DAC's commercially for a long time).
Again, it is not too hard to make up a test rig where you can feed the output of an audio generator into the supply line of the clock for a CDP, to get a similar result testing receivers for source jitter rejection.
🙂
Just don't expect it as an Open Source project.
I do have to feed the wife and children...
Ciao T
Then you might as well use a WM8804 in Hardware mode. It shows so dramatically lower output jitter (tested on AP2) compared to CS, it is not even funny. And yes, it is very audible compared to the CS. I recently had a chance to help a DAC Vendor to re-design his product for the WM instead of CS (all else remained in place) and it has been getting much increased sales and excellent reviews ever since.
The only reason not to use the 8804 is the funky behaviour at 176.4KHz but if you give that up anyway, you might as well use the 8804.
Oh, but make sure to give it a very clean low jitter reference clock. It seriously shows up.
There are other ways (arguably harder) to measure jitter, What AP adds most is a way to generate a precisely defined source jitter pattern which you can easily look for in the FFT of the output, so you can easily how well a receiver suppresses jitter (Hint, in case of the Cirrus Logic products - not all is the answer - hence I refused to make or get involved with DAC's commercially for a long time).
Again, it is not too hard to make up a test rig where you can feed the output of an audio generator into the supply line of the clock for a CDP, to get a similar result testing receivers for source jitter rejection.
🙂
Just don't expect it as an Open Source project.
I do have to feed the wife and children...
Ciao T
Well... If you don't want to do the FPGA programming i a open source project, I guess your suggestion is not that attractive 😉
About using WM8804, I see no problem, if this is what the people want. I has got some nice specifications.
We had several reasons for picking the CS8416. I have been working with CS chips for almost 15 years, and newer had any bad experience. I still remember when TI tried to launch an SPDIF receiver 😀
What we need of the SPDIF receiver is (The 3 most important):
1) Running i Hardware mode (We don't want a uC).
2) 2 and preferably 3 to 4 SPDIF inputs, available in HW mode.
3) Has to be available for the DIY users.
I have not yet checked, if WM8804 has got 2 inputs available in HW mode. Will go through the datasheet in a minute.
How about the availability??? I'm sure I can get samples for R&D directly from Wolfson. But how about the DIY users? Digikey do not stock Wolfson products. Mouser has got some, but as far as I can see, not the WM8804. One of the goals in this product is, to make it easy to source and build, not having to source from 15 different dealers. Where do you suggest to buy the Wolfson chips??
About using WM8804, I see no problem, if this is what the people want. I has got some nice specifications.
We had several reasons for picking the CS8416. I have been working with CS chips for almost 15 years, and newer had any bad experience. I still remember when TI tried to launch an SPDIF receiver 😀
What we need of the SPDIF receiver is (The 3 most important):
1) Running i Hardware mode (We don't want a uC).
2) 2 and preferably 3 to 4 SPDIF inputs, available in HW mode.
3) Has to be available for the DIY users.
I have not yet checked, if WM8804 has got 2 inputs available in HW mode. Will go through the datasheet in a minute.
How about the availability??? I'm sure I can get samples for R&D directly from Wolfson. But how about the DIY users? Digikey do not stock Wolfson products. Mouser has got some, but as far as I can see, not the WM8804. One of the goals in this product is, to make it easy to source and build, not having to source from 15 different dealers. Where do you suggest to buy the Wolfson chips??
Hi,
A commercial operation has already paid for my developments around SPDIF receivere etc., so I'm not at liberty to open-source the results.
Don't know what the "Ppee-pull" want, but if you want low jitter and sensible levels of source jitter suppression in a single chip, easy to implement, the WM8804/05 is the one to use right now. It is not really good enough for my tatse, but as said, it is three times better than the CS stuff on intrinsic stuff and around 100 times better (at 10KHz) than the CS stuff for source jitter.
Got that. Only fly in the ointment, no 176.4KHz in that mode. You need a MCU to control the Chip to get 176.4KHz to lock correctly. Which generally turns me off using the part, if I have to program anyway or pay someone to do it for me (more likely), I might as well use something else.
No HW selectable inputs, but excellent multiplex Chips exist for very little money, relays are possibly even better, with care you can keep the impedance very well under control and you can get ones with defined charatristic impedance.
I personally would transformer isolate the the SPDIF inputs anyway (the trick here is not to get an expensive "name brand" item, but to understand the parasitics of the transformer and to handle them correctly.
And I would use use some active circuitry to buffer the inputs of the chips (which are always schmitt triggers that kick glitches back into the cable on switching if connected directly) so the input cable is unaffected. Again, see "Jocko Homo" on the subject, he kind of wrote the book. It is not hard to implement.
Last time I looked, the 8804/05 was very easy to source. The 8805 is basically the same chip, but with 8:1 Multiplexer build in, but needs MCU to control the chip for input selection.
Farnell is where I usually buy stuff, or RS-Components.
Again, the 8804/05 uses an on board clock as the overall reference (but does not perform any ASRC function) and this clock is quite critcal. It achieves better than the 50pS from the datasheet with a really low jitter clock.
Ciao T
A commercial operation has already paid for my developments around SPDIF receivere etc., so I'm not at liberty to open-source the results.
Don't know what the "Ppee-pull" want, but if you want low jitter and sensible levels of source jitter suppression in a single chip, easy to implement, the WM8804/05 is the one to use right now. It is not really good enough for my tatse, but as said, it is three times better than the CS stuff on intrinsic stuff and around 100 times better (at 10KHz) than the CS stuff for source jitter.
Got that. Only fly in the ointment, no 176.4KHz in that mode. You need a MCU to control the Chip to get 176.4KHz to lock correctly. Which generally turns me off using the part, if I have to program anyway or pay someone to do it for me (more likely), I might as well use something else.
No HW selectable inputs, but excellent multiplex Chips exist for very little money, relays are possibly even better, with care you can keep the impedance very well under control and you can get ones with defined charatristic impedance.
I personally would transformer isolate the the SPDIF inputs anyway (the trick here is not to get an expensive "name brand" item, but to understand the parasitics of the transformer and to handle them correctly.
And I would use use some active circuitry to buffer the inputs of the chips (which are always schmitt triggers that kick glitches back into the cable on switching if connected directly) so the input cable is unaffected. Again, see "Jocko Homo" on the subject, he kind of wrote the book. It is not hard to implement.
Last time I looked, the 8804/05 was very easy to source. The 8805 is basically the same chip, but with 8:1 Multiplexer build in, but needs MCU to control the chip for input selection.
Farnell is where I usually buy stuff, or RS-Components.
Again, the 8804/05 uses an on board clock as the overall reference (but does not perform any ASRC function) and this clock is quite critcal. It achieves better than the 50pS from the datasheet with a really low jitter clock.
Ciao T
agree with ThorstenL, a lot of very good points.
@ThorstenL
have you tried to load down the rails with active elements (shunt type) after Teddy Reg instead resistors?
@ThorstenL
have you tried to load down the rails with active elements (shunt type) after Teddy Reg instead resistors?
Hi,
Personally I have been using Shunt Regulators fed by current sources fed by 3-Pin pre-regulators in all critical positions for many years (ever since Allen Wright propagandised me on shunt reg benefits), however complexity quickly escalates.
For example the clock supplies in the 96/24 USB ADC in my recent commercial Phono Stage uses 29 actual components and a separate supply winding (but manages 0.7nV|/Hz intrinsic noise). It also incorporates a number of R/L/C networks deliberately designed into the PCB layout to further improve on noise rejction at very high frequencies.
My suggestion of slightly modded Teddyregs was based on the fact that they work very well and are still acceptable in complexity, as I did not get the feeling this project was meant as all out assault on the state of the art.
Of course, one may add more components to the emitter follower to make it a very high impedance at AC (a virtual choke one may say) and to then use an active load to control the AC noise and impedance.
Once you sufficiently consequently pursue this concept you end up with my own regulators... And it is better than teddyreg and still of acceptable complexity.
But here a Sziklay Teddyreg with extra resistive loading is already at the limits the OP would likely accept.
Ciao T
Personally I have been using Shunt Regulators fed by current sources fed by 3-Pin pre-regulators in all critical positions for many years (ever since Allen Wright propagandised me on shunt reg benefits), however complexity quickly escalates.
For example the clock supplies in the 96/24 USB ADC in my recent commercial Phono Stage uses 29 actual components and a separate supply winding (but manages 0.7nV|/Hz intrinsic noise). It also incorporates a number of R/L/C networks deliberately designed into the PCB layout to further improve on noise rejction at very high frequencies.
My suggestion of slightly modded Teddyregs was based on the fact that they work very well and are still acceptable in complexity, as I did not get the feeling this project was meant as all out assault on the state of the art.
Of course, one may add more components to the emitter follower to make it a very high impedance at AC (a virtual choke one may say) and to then use an active load to control the AC noise and impedance.
Once you sufficiently consequently pursue this concept you end up with my own regulators... And it is better than teddyreg and still of acceptable complexity.
But here a Sziklay Teddyreg with extra resistive loading is already at the limits the OP would likely accept.
Ciao T
Nice to have some input for the project, but there is a point in keeping it on the ground.
We already did a project with 15 regulations of which 4 are shunts, and a complete NFB and discrete analog design, based on CS8416, AD1896 and CS4398.
This ended up in more than 400 components, 3 PCB´s and a price close to the double of this project.
The whole idea doing of the earlier project, was to examine which components are the most important ones, and where do you have to put you attention to get the highest possible payback in sound quality.
After a lot of prototypes, and hundreds of experiments with the surroundings to the chips and the analog stage, we have made some conclusions of which the majority (IMHO) is pretty logical and unidiosyncratic.
I´ll try to list a few of my findings, which i hope might be of some use.
Just my 5 cents
We already did a project with 15 regulations of which 4 are shunts, and a complete NFB and discrete analog design, based on CS8416, AD1896 and CS4398.
This ended up in more than 400 components, 3 PCB´s and a price close to the double of this project.
The whole idea doing of the earlier project, was to examine which components are the most important ones, and where do you have to put you attention to get the highest possible payback in sound quality.
After a lot of prototypes, and hundreds of experiments with the surroundings to the chips and the analog stage, we have made some conclusions of which the majority (IMHO) is pretty logical and unidiosyncratic.
I´ll try to list a few of my findings, which i hope might be of some use.
- In designing digital circuits, layout and powersupplies are cruisial.
Supplies are at best isolated from each other by separate regulators for each device, and even more regulation, if the device needs more than just one voltage.
- The Oscillator needs its own regulator.
- The analog stages in the chips need analog care in their supplies, which means absolutely no tantalums or ceramics in the decoupling.
- VREF, and FILT decoupling are extremely sensitive to cap quality on CS4398
- Also analog supply on CS8416 is very important, do not use ceramics for this.
- In analog design refuse to use caps in signalpath
- Do not use NFB if possible
- Keep capacitors away from power supply - use shunts without decoupling when possible
- When capacitors are unavoidable, use polyphenylene sulfid caps.
- Be aware that carefull analog design pays of much more sound quality than digital
- The digital components is by far the best in any DAC available anyway, the analog components can not at all provide DR and THD levels that digital circuits can.
- When it comes to jitter, jitter is best fought at the very source, which leads to pay attention to supplies in your source.
Try out very good decoupling at the very feet of the relevant components in your transport. (polyphenylene sulfid is my favourite)
- Keep the DAC as integrated and compact as possible
- Upsampling brings down jitter from hopefully a low level to almost nothing if done carefully
- Stay true to 75 Ohm transmissionline
Just my 5 cents
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Hi,
Shunts are killers - yoy are so right😀
We also used current sources to feed them🙂
Ciao T
Shunts are killers - yoy are so right😀
We also used current sources to feed them🙂
Sounds nice
As mentioned, we did that already in the earlier project
No offence, but I think you overestimate DIYérs generaly, and please think of availabillity to.
Ciao T
Hi Kurt von Kubik, 🙂
This is unexpected. Also, many datasheets and application notes (especially at analog.com) recommend using ceramics in combination with tantalum capacitors for filtering the power supplies of high quality opamps. On what base you have concluded that ceramics and/or tantalums are not good for power supply filtering?
Cheers
Hi,
I agree with most, except:
More than that, a separate supply winding is highly recommended. And consider how to get the clock signal into the chip it drives, as there is the not so minor issue of the ground (and supply) bounce from bondwire and leadframe resistance/inductance.
I would have thought you would by now have tried discrete active reference generators. I found that these make a quantum leap in performance on any DAC chip that has externally available reference pins.
I disagree. If your analogue design and your supplies etc is up to scratch even seemingly minor digital design issues (such as the exact waveshape on the digital input pin's) become quite audible.
True, if your analogue design is below par these improvements will not count, but given how easy decent analogue design is nowadays (even op-amp's selected and applied well are good enough) this is not an excuse.
But having excessive jitter or other design issues in the digital side very quickly brickwalls performance at well below what is possible to attain.
!!?? I can toss off analogue circuits that are massively better than -107dB THD&N and 120dB SNR in a jiffy. Even most affordable Op-Amp's do better. So I disagree. The digital section is a major headache and getting it right needs usually quite heroic measures.
Due to a range of issues intrinsic to the SPDIF system there are hard limits. Thanks to ground loops (which transformers would arguably reduce) and the lowpass behaviour of our cable it is difficult to reliably have sub 1nS jitter in a SPDIF systems, unless the receiver can filter that jitter out. To filter this jitter requires a low noise VCO and a slow PLL - Philips & Marantz knew that back in the 80's when they designed the LHH-1000 aka CD-12/DA-12 combo.
There are as mentioned ways around this, but they all involve in one way or the other separating the clock and data. In this case the general compatibility of the DAC is removed and we may as well make a CD-Player, which is at least commercially what I have done so far.
For a DAC we must kill the jitter in the receiver (though reducing it as much as possible in the source also helps) or follow a generic high jitter receiver with a secondary PLL or DLL with a sub Hz cutoff.
The best I have been able to achieve with optimised source and optimised CS Receivers with added "clever" input circuitry was still worse than the resolution of my DAC Chip (suggesting around 200-300pS Jitter for the whle system including source) meaning I lost dynamic range available from the DAC due to jitter.
On the other hand, with the same DAC in a CD-Player with good clocking system (no SPDIF) I get all the DR the DAC offers. With a receiver system that "locks out" jitter correctly I find the limit is that of the final reclocker flip flops and the clock itself, a total of a few tens pS, so good enough for more than 16 Bits...
Upsampling forces the jitter to leave the time-domain, so it no longer directly shows up as jitter, when we look for JITTER. So where is it gone? Is it gone for good? Nope, it is now embedded in the signal as PIM and IM and other forms of distortion that CANNOT be removed, unlike time domain jitter, which can actually be filtered very effectvely (if not too simply).
Of course, if using Delta Sigma DAC's (which are inordinately sensitive to jitter on their system clock) this may be preferable to allowing the jitter from a poor receiver circuit through, but "upsampling" in this case remains a very poor band-aid that glosses over the underlying problem and in the process adds it's own artifacts.
It is very illuminating to hear ASRC routines employed where they have no jitter to clean up, but are strictly "upsampling" and where the systems time domain jitter of the system is properly under control. There are two CD-Players that allow exactly this and all those who tried prefer to switch upsampling (and indeed oversampling) off.
Ciao T
PS, someone mentioned the Tenor Chips for USB, they are not bad, around the same level of jitter as the Cirrus Logic receivers and hence notably better than the TI stuff if build to datasheet, which in turn beats the stuffing out of C-Media's CM108. Shame the Tenor stuff only does 32/44.1/48/96 so that even 88.2KHz must be resampled.
My personal (DIY) choice in USB source are modifications based on the Musiland Devices. Transparent sample rate handling up to 192KHz, fully asynchronous protocol and if fitted with a decent powersupply and clock sub 200pS jitter, at least as good as any CDP/Transport I know.
I agree with most, except:
More than that, a separate supply winding is highly recommended. And consider how to get the clock signal into the chip it drives, as there is the not so minor issue of the ground (and supply) bounce from bondwire and leadframe resistance/inductance.
I would have thought you would by now have tried discrete active reference generators. I found that these make a quantum leap in performance on any DAC chip that has externally available reference pins.
I disagree. If your analogue design and your supplies etc is up to scratch even seemingly minor digital design issues (such as the exact waveshape on the digital input pin's) become quite audible.
True, if your analogue design is below par these improvements will not count, but given how easy decent analogue design is nowadays (even op-amp's selected and applied well are good enough) this is not an excuse.
But having excessive jitter or other design issues in the digital side very quickly brickwalls performance at well below what is possible to attain.
!!?? I can toss off analogue circuits that are massively better than -107dB THD&N and 120dB SNR in a jiffy. Even most affordable Op-Amp's do better. So I disagree. The digital section is a major headache and getting it right needs usually quite heroic measures.
Due to a range of issues intrinsic to the SPDIF system there are hard limits. Thanks to ground loops (which transformers would arguably reduce) and the lowpass behaviour of our cable it is difficult to reliably have sub 1nS jitter in a SPDIF systems, unless the receiver can filter that jitter out. To filter this jitter requires a low noise VCO and a slow PLL - Philips & Marantz knew that back in the 80's when they designed the LHH-1000 aka CD-12/DA-12 combo.
There are as mentioned ways around this, but they all involve in one way or the other separating the clock and data. In this case the general compatibility of the DAC is removed and we may as well make a CD-Player, which is at least commercially what I have done so far.
For a DAC we must kill the jitter in the receiver (though reducing it as much as possible in the source also helps) or follow a generic high jitter receiver with a secondary PLL or DLL with a sub Hz cutoff.
The best I have been able to achieve with optimised source and optimised CS Receivers with added "clever" input circuitry was still worse than the resolution of my DAC Chip (suggesting around 200-300pS Jitter for the whle system including source) meaning I lost dynamic range available from the DAC due to jitter.
On the other hand, with the same DAC in a CD-Player with good clocking system (no SPDIF) I get all the DR the DAC offers. With a receiver system that "locks out" jitter correctly I find the limit is that of the final reclocker flip flops and the clock itself, a total of a few tens pS, so good enough for more than 16 Bits...
Upsampling forces the jitter to leave the time-domain, so it no longer directly shows up as jitter, when we look for JITTER. So where is it gone? Is it gone for good? Nope, it is now embedded in the signal as PIM and IM and other forms of distortion that CANNOT be removed, unlike time domain jitter, which can actually be filtered very effectvely (if not too simply).
Of course, if using Delta Sigma DAC's (which are inordinately sensitive to jitter on their system clock) this may be preferable to allowing the jitter from a poor receiver circuit through, but "upsampling" in this case remains a very poor band-aid that glosses over the underlying problem and in the process adds it's own artifacts.
It is very illuminating to hear ASRC routines employed where they have no jitter to clean up, but are strictly "upsampling" and where the systems time domain jitter of the system is properly under control. There are two CD-Players that allow exactly this and all those who tried prefer to switch upsampling (and indeed oversampling) off.
Ciao T
PS, someone mentioned the Tenor Chips for USB, they are not bad, around the same level of jitter as the Cirrus Logic receivers and hence notably better than the TI stuff if build to datasheet, which in turn beats the stuffing out of C-Media's CM108. Shame the Tenor stuff only does 32/44.1/48/96 so that even 88.2KHz must be resampled.
My personal (DIY) choice in USB source are modifications based on the Musiland Devices. Transparent sample rate handling up to 192KHz, fully asynchronous protocol and if fitted with a decent powersupply and clock sub 200pS jitter, at least as good as any CDP/Transport I know.
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Hi,
Well, my own designs mentioned are using only extremely generic components (they must be reliably manufacturable in series production). Availability is as much an issue.
And the idea in this project I though was to give DIY'ers a set of PCB's together with a shopping list and have them to solder the stuff together? If so, then they do not need to understand or design the circuitry, all they need to do is to solder resistors, capacitors and BC550/560 and BD139/140 in place.
Given that you include SMD chips in the design which are hard to solder by hand I would not worry about a few discrete parts.
Ciao T
Well, my own designs mentioned are using only extremely generic components (they must be reliably manufacturable in series production). Availability is as much an issue.
And the idea in this project I though was to give DIY'ers a set of PCB's together with a shopping list and have them to solder the stuff together? If so, then they do not need to understand or design the circuitry, all they need to do is to solder resistors, capacitors and BC550/560 and BD139/140 in place.
Given that you include SMD chips in the design which are hard to solder by hand I would not worry about a few discrete parts.
Ciao T
FPGA spdif receiver
Thorsten,
Working this way, I suppose you work edge-triggered and not by "over"-sampling the incomming spdif signal, correct?
Initially I was thinking to use 30-40MHz oversampling of the input signal, using embedded block-Ram (MachXO from Lattice would allow a +/- 128 stereo sample buffer) as dual clocked FIFO with a local audio clock to read-out the samples from the FIFO. At digital silence you can again fill the FIFO optimally.. but all this might generate a bit too much noise in the receiver circuitry (I'm digesting all the info from ECdesigns).
I have been looking for a good example for a VCXO application, only usable thing I found is: http://members.chello.nl/~m.heijligers/DAChtml/dig_r2c.pdf
Is this a good start, any comment, do you have other examples?
Thanks!
Thorsten,
Working this way, I suppose you work edge-triggered and not by "over"-sampling the incomming spdif signal, correct?
Initially I was thinking to use 30-40MHz oversampling of the input signal, using embedded block-Ram (MachXO from Lattice would allow a +/- 128 stereo sample buffer) as dual clocked FIFO with a local audio clock to read-out the samples from the FIFO. At digital silence you can again fill the FIFO optimally.. but all this might generate a bit too much noise in the receiver circuitry (I'm digesting all the info from ECdesigns).
I have been looking for a good example for a VCXO application, only usable thing I found is: http://members.chello.nl/~m.heijligers/DAChtml/dig_r2c.pdf
Is this a good start, any comment, do you have other examples?
Thanks!
To pass the spdif on to a chip that has a single spdif input, such as some of ESS chips. The Wolfson chip will select the signal, clean it up and pass it on to the chip.
I don't know if the multi-spdif input ESS chips need a comparator on the spdif lines. Have not yet seen the datasheets.
Hi,
The analogue supplies are extremely sensitive on this chip, the stock op-amp circuitry is at best so-so... Discrete super low noise shunts are another story.
Please use the outputs in current-mode, not voltage-mode, it sound significantly better. Then follow with a discrete differential with 2SK389BL/LSK389B, BJT cascoded. This would give very close to best noise and linearity in non-nfb circuit. The rest would be straight forward.
The ESS Sabre also needs care for the (40MHz) clock and sounds even better if you feed it with low jitter I2S signals than when fed jittery SPDIF.
Also, the ESS can be loaded with custom digital filters. Find someone to help write a minimum phase, apodising filter to load up.
Make the thing for 200 bucks, heck, I'll sign up for the first PCB GB, just for fun!
As for 32 Bit, it is well off the scale on my **'o'meter but there is a reason, M$'s latest audio formats and "HD" subsystems use 32 Bit files/formats, even if we struggle producing a real 18 to 19 Bit analogue resolution and even if most mikes only have less than 18 Bit equivalent usable dynamic range.
Ciao T
The analogue supplies are extremely sensitive on this chip, the stock op-amp circuitry is at best so-so... Discrete super low noise shunts are another story.
Please use the outputs in current-mode, not voltage-mode, it sound significantly better. Then follow with a discrete differential with 2SK389BL/LSK389B, BJT cascoded. This would give very close to best noise and linearity in non-nfb circuit. The rest would be straight forward.
The ESS Sabre also needs care for the (40MHz) clock and sounds even better if you feed it with low jitter I2S signals than when fed jittery SPDIF.
Also, the ESS can be loaded with custom digital filters. Find someone to help write a minimum phase, apodising filter to load up.
Make the thing for 200 bucks, heck, I'll sign up for the first PCB GB, just for fun!
As for 32 Bit, it is well off the scale on my **'o'meter but there is a reason, M$'s latest audio formats and "HD" subsystems use 32 Bit files/formats, even if we struggle producing a real 18 to 19 Bit analogue resolution and even if most mikes only have less than 18 Bit equivalent usable dynamic range.
Ciao T
+10, if quality is in the first place than all that you can use is only IIS bus or SPDIF from 8804 (or similar PLD design)
and dont use 4398, it is very easy to use dac but the quality is not good, really not good...
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Hi,
The actual spdif decoder is primitive. the key is a big buffer and the logic to observe the buffer state to see if it grows, shrinks or is at halve full. Then adjust the VCXO.
Something like this will be doable, but 128 samples get used up incredibly quickly.
Jos van Eijndhoven - DAC2
This principle could be done fully on the FPGA without MCU and could use external R2R resistor networks to create the DAC.
That is the way to do it "DIY". If you go for hardcore production units it is probably easier to use a MCU core to program a nice mil spec programmable low jitter clock oscillator and have the detector part in the FPGA. Well, I already said too much I guess.
Ciao T
The actual spdif decoder is primitive. the key is a big buffer and the logic to observe the buffer state to see if it grows, shrinks or is at halve full. Then adjust the VCXO.
Something like this will be doable, but 128 samples get used up incredibly quickly.
Jos van Eijndhoven - DAC2
This principle could be done fully on the FPGA without MCU and could use external R2R resistor networks to create the DAC.
That is the way to do it "DIY". If you go for hardcore production units it is probably easier to use a MCU core to program a nice mil spec programmable low jitter clock oscillator and have the detector part in the FPGA. Well, I already said too much I guess.
Ciao T
Hi,
The guys until 10 minutes ago where set on the 4398... I already upset them too much as is, so I left them the 4398... 😀
Ciao T
The guys until 10 minutes ago where set on the 4398... I already upset them too much as is, so I left them the 4398... 😀
Ciao T
Can you elaborate on this please? The ESS chip is supposed to clean up the SPDIF signal, and I've found that it seems to do well.
What sort of tests have you done to show that a low jitter I2S signal sounds better than the SPDIF?
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