I decided to post my schematic. As I said, I make no claims as to originality, and I'm not really interested in hearing about why it sucks.
Referring to these generic diagrams (full schematic is below):
Breaking the feedback loop, applying a voltage Vi to the non-inverting input results in a current In = Vi / Rg flowing out of the inverting terminal. This current is mirrored to the output load impedance Zo, producing an output voltage Vo = In * Zo. It follows that the open-loop voltage gain is just Aol = Zo / Rg. In my circuit, at DC, this is 200 * log(100K / 332) = 49.6dB.
Connecting the feedback resistor Rf, a feedback current If = (Vo - Vi) / Rf flows back into the inverting input. Loop gain is just the difference between Aol and Acl. With a little math, you can show that the loop gain is given by |T| = Zo / Rf. At DC, this is just 20 * log(100K / 332) = 42.5dB. There is a dominant pole in the open-loop response at frequency 1 / (2 * pi * Rl * Cdom) = 33.9 kHz. This is confirmed by the SPICE Bode plot. Closed-loop gain is 1 + (Rf / Rg) = 1 + (750 / 332) = 3.26. We lose a little in the input divider network; call the final closed-loop gain 10 dB.
Closed-loop bandwidth is the frequency where the loop gain falls to unity, around 2 MHz. Increasing Rf raises the closed-loop gain and lowers the closed-loop bandwidth. On the other hand, if we change the closed-loop gain by varying Rg, the closed-loop bandwidth remains the same. This is because both the open- and closed-loop gains are affected equally by Rg (on a log scale). As we change Rg, the two curves rise or fall by the same amount, and the frequency where they intersect stays constant.
There's obviously a limit to how far we can go with this since the input buffer output impedance is non-zero. That is, we can't get infinitely high open-loop gain by setting Rg to zero. There are some practical limits on the value of Rg. Intuitively, values around ten times the buffer output impedance seem to make sense.
From a design standpoint, we might start by deciding how much loop gain (feedback) we want. I arbitrarily picked 40 dB with the intent of maybe drying up the sound a little bit compared to the HPA-1. It's unclear why Zo is set so low (4.7K | 4.7K = 2.35K) in the Pass Labs amplifier. Perhaps this is to swamp the nonlinear input capacitance of the MOSFET output stage, or maybe it was just selected by ear. Lower values of Zo mean correspondingly higher currents flow out of the driver stage. The diamond buffer output stage in the new design presents a friendlier input load, so I set the driver load resistor at 100K. It follows that Rf = 750 Ohms gets us close to our 40 dB loop gain target.
From there, we can select the value of Cdom. There's plenty of phase margin, so I picked 47pF. This is about fifteen times lower than the combined capacitive load seen by the A3 driver. Open-loop frequency response is flat across the audio band, which some people think is a good thing. I am adopting a distinctly anti-Self approach here of not trying to maximize midband NFB.
Slew rate is less of a problem in a CFA because the Cdom charging current comes from the feedback network. But I couldn't think of a good reason to use a larger capacitor, which would require lowering resistor values all around to get to my open-loop gain and bandwidth targets.
I have cribbed the DC servo from the HPA-1 clone. The stock servo output resistor is given as 150K. This is relatively high, presumably to minimize interaction of the audio signal with the servo. This means the op-amp will have to swing a correspondingly larger voltage to cancel a given output offset. I reduced the value to 100K in this design because my rail voltages are lower and I don't want the servo amp to run out of voltage headroom. In practice, it shouldn't matter.
I have added my driver stage regulators, just because. These devices are unavailable right now, but I have a stash of them. A capacitance multiplier would be easier to source parts for, and would be more in keeping with the HPA-1 design philosophy. But I was lazy and didn't feel like solving another layout problem. And this is not an HPA-1.
I've also added an input ultrasonic filter. It may not be needed in a CFA, and the HPA-1 doesn't have one. But I don't see the point of extending wide-open arms to RF at the input, so there you go.
I changed the output transistors from KSA1220/KSC2690 (in the A3) to TTA/TTC004B. In the SPICE simulation, the KSA1220 is doing a weird thing where the base-emitter junction breaks down at higher output currents. The TTA004B does not exhibit this behavior, and I saw no issue on the bench with the A2. The TTA/TTC parts are still in production, whereas the KSA1220 is not (though I have some on hand). The KSA/KSC parts are rated for higher Ft, but the former devices are plenty fast enough for this application.
I debated getting rid of the output diamond cross-coupling connections on account of the very low collector-emitter voltage (~1.2V) available to Q11 and Q13. But the TTA/TTC004B are specified for a low saturation voltage and the output stage works fine in the A1/A2. Cross-coupling reduces simulated distortion by a small margin, so I decided to leave the cross-coupling as-is. I did not cross-couple the input diamond buffer because it doubles the current in Q9 and Q14 with no apparent improvement in overall distortion.
I tossed the output inductor because the amplifier is not significantly affected by capacitive output loads on account of the generous phase margin. Similarly, the output Zobel network doesn't do much in the simulator, but I left it in as a reflex.
I set all the mirror emitter resistors to 100 Ohms as I saw no need for current gain in the middle stage mirror (as used in the HPA-1). I moved the offset trimpot to the junction of the input buffer emitter resistors because I like the symmetry. You can debate the sonic horrors of passing the feedback signal through a potentiometer wiper, but I won't worry about it.
The whole thing hangs together nicely in SPICE with a clean square wave response and no tendency to misbehave with capacitive loads, or under clipping. The distortion plot above was at 1.5VRMS output into 32 Ohms. Distortion products rise with higher output voltages, as is the case with the HPA-1 measurements published by Stereophile. Simulated THD is under 0.01%, and more like 0.001%, under most operating conditions.
You could argue that this whole exercise is pointless since there is no hope of my bettering the HPA-1. Still, if I can get the parts, I will build this soon. I expect it will sound fine. Since I have another chassis ready to go, I will have three physically similar headphone amplifiers, and only one pair of ears. I can't complain about the sound of the A2 and A3 (or the A1, for that matter). Perhaps I will put some of these amps up for sale, dunno. I will probably just put the A1 PC boards in plastic bags and throw them in my bedside table drawer, along with the DCG3 board.
I have put my Kicad files on GitHub:
https://github.com/hapasternack/A4. I'm not soliciting contributions, but I suppose if anyone wants to suggest improvements you can send me pull requests and I will look at them. I will report on my progress with this project, but will leave my cat to respond to any naysayers.
The cat was looking over my shoulder the other night while I worked on this, and smirking. I asked him what was so funny, but he just shook his head and refused to say anything. I told him if he didn't have anything nice to say, he could keep it to himself. He just smirked some more and started chewing on the cable to my soldering iron. So I ignored him.
