Sebastien,
You are 100% correct. Those diodes should be back to back, and across the 220uF shunt fb cap.
Dave,
As frequency rises, the input impedance to the base of the VAS drops, and the local feedback via the Miller cap reduces gain. These conspire to increase distortion, no?
Cheers,
Hugh
You are 100% correct. Those diodes should be back to back, and across the 220uF shunt fb cap.
Dave,
As frequency rises, the input impedance to the base of the VAS drops, and the local feedback via the Miller cap reduces gain. These conspire to increase distortion, no?
Cheers,
Hugh
Greg Erskine said:
Dave, interested. I've been thinking the same thing but wouldn't it be equally as good for the input transistors. I think I read years ago that JC does something to stop the flow of air around the transistors to keep the transistor temperature constant.
I was thinking the transitors should be buried in the main heatsink and internal air flow restricted. The main heatsink would need to be reduced in size the increase temp a little. Poor capacitors.
Alex's amp probably already runs at greater than 55C.
regards
G'day Greg,
Trust all's well.
I have some PTR's and I'm going to use a modded version of the Jaycar temp switch kit. I should be able to hold temp to within 1 degree C.
Keeping LTP's constant might be usefull in some designs but in this design the LTP temperature has really no effect on gm and the tail current is determined by the active current source which is already temperature compensated. In any case the LTP are usually sailing close to the wind with 50V rails and 3mA so extra heating is not recommended.
Also, I'm trying to be as green as possible (within reason). For a 100W amp my E ULD runs very cool. I'm trying to keep it Peter Garrett friendly.
Cheers,
Dave
I think you have misunderstood Self's advice.
I have edition 2 so all my references date back to that revision.
Fig 2.6 plots the distortion comparison between no output capacitor and 6800uF feeding an 8r0 load.
The F-3dB of this 6800uF 8ohm combination is ~2.9Hz. The graph shows that distortion rises through the whole audio bandwidth, when capacitor coupled.
But, very significantly shows an upward slope below 50Hz.
He then swaps the 6800uF to 100mF and compares the two before and after plots, Fig 2.7.
This has moved the F-3dB down by a factor ~15 to ~0.2Hz. The comparison is very illuminating.
He then shows the comparison using a 4700uF cap and the upward slope now starts at ~200Hz, fig2.8.
This all relates to output capacitor coupling, but I feel that this is the introduction to the chapter on the effects of the NFB cap (distortion 8).
Fig 6.14 shows the distortion rising from ~140Hz and this corresponds to the graph, fig6.15, showing the LF roll off associated with the NFB cap and it's -0.7dB @ 10Hz.
He goes on to say
Further on he says
He confirms how to achieve this elimination of feedback capacitor distortion (in AC coupled amplifiers)
At no time has he mentioned that the protective diode/s play any part in eliminating this LF distortion.
The whole mechanism depends on filtering the input to prevent any AC voltage across the NFB capacitor. No AC voltage is equivalent to no capacitor distortion. It's all achieved by sizing the DC blocking capacitors appropriately.
The input filter of fig6.16 is set to Rc=0.1s the NFB filter is set to RC=0.15s i.e. NFBrc >= sqrt(2)*INPUTrc.
The diode/s are there to limit the fault voltages that could damage the capacitor and/or the input stage. They are not placed there to reduce distortion.
I have edition 2 so all my references date back to that revision.
Fig 2.6 plots the distortion comparison between no output capacitor and 6800uF feeding an 8r0 load.
The F-3dB of this 6800uF 8ohm combination is ~2.9Hz. The graph shows that distortion rises through the whole audio bandwidth, when capacitor coupled.
But, very significantly shows an upward slope below 50Hz.
He then swaps the 6800uF to 100mF and compares the two before and after plots, Fig 2.7.
This has moved the F-3dB down by a factor ~15 to ~0.2Hz. The comparison is very illuminating.
He then shows the comparison using a 4700uF cap and the upward slope now starts at ~200Hz, fig2.8.
This all relates to output capacitor coupling, but I feel that this is the introduction to the chapter on the effects of the NFB cap (distortion 8).
Fig 6.14 shows the distortion rising from ~140Hz and this corresponds to the graph, fig6.15, showing the LF roll off associated with the NFB cap and it's -0.7dB @ 10Hz.
He goes on to say
This implies that using a large enough capacitor eliminates the feedback capacitor distortion.
Further on he says
He confirms how to achieve this elimination of feedback capacitor distortion (in AC coupled amplifiers)
He implies that the degraded distortion evident at 10Hz is not good enough and the suggested value for C2 is 220uF to eliminate distortion8.
At no time has he mentioned that the protective diode/s play any part in eliminating this LF distortion.
The whole mechanism depends on filtering the input to prevent any AC voltage across the NFB capacitor. No AC voltage is equivalent to no capacitor distortion. It's all achieved by sizing the DC blocking capacitors appropriately.
The input filter of fig6.16 is set to Rc=0.1s the NFB filter is set to RC=0.15s i.e. NFBrc >= sqrt(2)*INPUTrc.
The diode/s are there to limit the fault voltages that could damage the capacitor and/or the input stage. They are not placed there to reduce distortion.
Andrew,
I use Black Gate NX caps in this position, with very low VW rating. I put back to back diodes across them simply to protect them in the event of an output device failure, where the fb node would otherwise swing to the rail voltage/gain.
Since this cap has very low ESR, the AC voltage across it is also very low, in fact any AC voltage across it is in fact distortion artefacts, as you point out. Thus Self's argument that the cap should be large to avoid the characteristic THD rise at LF is on the money.
In most jfet designs, this cap may be eliminated. I'm not aware of any documented evidence that the absence of an electro in this position improves SQ, but I'm all ears....
Cheers,
Hugh
I use Black Gate NX caps in this position, with very low VW rating. I put back to back diodes across them simply to protect them in the event of an output device failure, where the fb node would otherwise swing to the rail voltage/gain.
Since this cap has very low ESR, the AC voltage across it is also very low, in fact any AC voltage across it is in fact distortion artefacts, as you point out. Thus Self's argument that the cap should be large to avoid the characteristic THD rise at LF is on the money.
In most jfet designs, this cap may be eliminated. I'm not aware of any documented evidence that the absence of an electro in this position improves SQ, but I'm all ears....
Cheers,
Hugh
AKSA said:
Hugh,
From a THD pov the EF seems to give the best bang for buck between LTP and VAS. There was some good info published by Self in EWW (and in his bible) which you may already have. By boosting the current gain the output impedance of the VAS is made small (xc / beta) By making beta > 20000 it's possible to reduce VAS output impedance to < 50 ohms at 2 KHz. You have probably achieved similar with your CFP VAS too but whether it accounts for the same level of SQ improvment as I've heard with blameless designs I don't know. But it definitely can't hurt.
Self found that buffering the VAS also reduced distortion but not quite to the same extent. Also, the more EF stages you have following the VAS the more you need to stabilise - assuming you use conventional bias gen from the VAS itself.
Another bonus with the EF beta booster is that the LTP is probably loaded with less miller capacitance because the device need only be small signal TO-92.
You are very correct to recommend substituting the bc 639 in the E-ULD200. That's really a poor choice by the SC design team.
Well not really my thoughts alone but who am I to disagree with with Mr Self. He was also attempting to design the simplest and least expensive amplifier. I'm sure there are much better designs but they would probably be much more complex. On the other hand it's reassuring to know that Candy's $50,000 Halcro's also resemble Self's 3 stage model.
FWIW the latest Krells do not employ class A but instead use high bias class A driver stages (very low Z out) to fully isolate the VAS from the crossover region. Perhaps that's a direction we could take the E-ULD200 - in due course. The self contained diode biasing of the output stage would make it more simple to implement a high bias class A driver stage. I'm thinking triple darlington with nested FB and dedicated bias control.
V2.0c ULD shows a string of 4diodes and a variable resistor (100r) along with 6NJLs.
Could a fifth and sixth diode be brought into the string but appearing in parallel to the VR?
The one or two extra diodes can easily be shorted out with a link if the builder does not want to use them.
The 100r can be any value from 100r to 20k.
This would allow the tempco to be dialled in by reduce the effect of the fifth diode by bypassing it with the VR.
None of this would take up any extra PCB space. It would increase enormously the options open to the first few builders, who could then advise the later builders on which options seem to work best.
I am sorry if this seems a repeat of what I said before, but it's a no cost option that has been ignored.
Could a fifth and sixth diode be brought into the string but appearing in parallel to the VR?
The one or two extra diodes can easily be shorted out with a link if the builder does not want to use them.
The 100r can be any value from 100r to 20k.
This would allow the tempco to be dialled in by reduce the effect of the fifth diode by bypassing it with the VR.
None of this would take up any extra PCB space. It would increase enormously the options open to the first few builders, who could then advise the later builders on which options seem to work best.
I am sorry if this seems a repeat of what I said before, but it's a no cost option that has been ignored.
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.