Yeah, I would say so. Its something to keep in mind.
BTW, the reason white noise can vary so much is because white noise may be defined by the flat spectrum of the noise frequencies' magnitudes. What makes white noise be able to take on so many different forms in the time domain is the relative phases of the noise frequencies. The relative phases depend on the nature of the physical process that creates the noise in the first place.
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For some ferrite beads, you need to cut the inductance in parts that each get their own parallel resistance to model the real and imaginary part of the impedance reasonably well. Two parts are usually enough to get within 10 % for most frequencies.
Hysteresis distortion/noise has been modeled, measured, and listened to. For a steady state sine wave you will see FFT spurs, since the minor hysteresis loop keeps retracing the same path. However, the particular hysteresis loop path may be frequency and signal level dependent. For non-steady state signals its more complicated.
For a dac clock, whatever can be measured on the clock power rail may or may not matter if the end purpose is to predict whether any resulting effect is expected to be audible to some or all of the population of potential dac customers. This assumes that the dac is for human listening use of course.
Other people have already done some work on that question, with unfortunately not a whole lot of it having been published. IIRC, @ThorstenL used his employees for listening test duty. Again IIRC, he talked about the sound of clock jitter affecting a dac audio output being a function of the RMS value of jitter for each offset frequency.
However, how particular types of noise on an oscillator power rail induce particular jitter may vary from one oscillator design to another.
IOW, looks like a lot of potential research is possible in this area, probably considerably more than simple modeling in matlab could substitute for.
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IMO the biggest mistake you can make is to get stuck on details at the beginning. Better to design and even implement a first iteration or prototype of the whole. It is much easier to have a working prototype to find out what really needs tuning. Another thing is that you need to separate facts from opinions. It is quite easy to come up with various details that may potentially have an impact. Better to find out in practice and through experience which of those really do make a difference.
Agreed. Plan on designing so some experiments can be performed later, but keep it moving along for now.
I can't enjoy my jazz recording because the trumpet player is slightly to the right of where I imagine he should be.
Do I need to adjust the value of a capacitor or something?
The question is: If you hear a difference in imaging between two pieces of audio equipment, which is correct?
How do you determine the point of reference, keeping in mind that all of the electronics used in the recording chain was less than perfect.
Knowing how a 4493, 4497, 4499, etc. should measure with a proper circuit design and PCB layout, it is best to use your APx555 (or whatever analyzer you have on hand) to validate your design, For example if your new 4499 design isn't doing better than -120dB THD+N, something is wrong. Conversely, if it is doing better than -120dB, it means that you have probably crossed your T's and dotted your I's.
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No.
For examples, most DACs are very sensitive to any modulation of VREF.
That would immediately show up on the AP.
For examples, most DACs are very sensitive to any modulation of VREF.
That would immediately show up on the AP.
What if its random noise on Vref? What does that look like on the AP? (@bohrok2610, please don't answer for him.)
Progress! I'm still thinking about OPAMP.
1. Discrete
2. FDA Buffer(?) by Altor
3. dual OPAMP IC like bohrok's AK4490.
-JTAG, I2C, SPI, and several GPIOs are integrated into a 2x10 pin header.
-changed the clock to the cheaper and smaller NZ2520. IMHO Since the NZ2520 is in standby mode, it maximizes the benefits of local LDO.
Or can use Si570. But, some DIYers point out that the Si570 has poor jitter performance.
1. Discrete
2. FDA Buffer(?) by Altor
3. dual OPAMP IC like bohrok's AK4490.
-JTAG, I2C, SPI, and several GPIOs are integrated into a 2x10 pin header.
-changed the clock to the cheaper and smaller NZ2520. IMHO Since the NZ2520 is in standby mode, it maximizes the benefits of local LDO.
Or can use Si570. But, some DIYers point out that the Si570 has poor jitter performance.
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Maybe you should just work on planning the schematic before working too much on a conceptual layout. Sometimes electrical requirements should be considered first, before board visual aesthetics. Just sayin'
Still in progress.
-All terminals are replaced with USB C type.
USB 2.0: USB4110-GF-A
POWER: USB4135-GF-A
(GCT site has a user-friendly UI, only one attractive option, and simple numbering.)
-The LT3471 has been replaced by the relatively inexpensive and more modern solution, the TPS65131.
-The output stage follows the suggestion of altor.
However, opa1632 is replaced by opa1633, lme is replaced by opa1612,
The vref cap is designed to use vishay's 293D footprint and is designed to be 10~22uF. The additional bypass is NP0 100n+10n.
Also, I am conside lowering the order of the LPF by one step.
-If know of a good flip-flop (for MLCK/2), please recommend it.
Current candidates are 74LVC1G80 or 79.
-All terminals are replaced with USB C type.
USB 2.0: USB4110-GF-A
POWER: USB4135-GF-A
(GCT site has a user-friendly UI, only one attractive option, and simple numbering.)
-The LT3471 has been replaced by the relatively inexpensive and more modern solution, the TPS65131.
-The output stage follows the suggestion of altor.
However, opa1632 is replaced by opa1633, lme is replaced by opa1612,
The vref cap is designed to use vishay's 293D footprint and is designed to be 10~22uF. The additional bypass is NP0 100n+10n.
Also, I am conside lowering the order of the LPF by one step.
-If know of a good flip-flop (for MLCK/2), please recommend it.
Current candidates are 74LVC1G80 or 79.
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-This new split rail circuit outputs +/-12V.
- 5V to 6V for -5V (VDDL/R) uses TPS61252DSGT.
-In the case of -3.3V, 5V is supplied to the LDO through a 1000uF reservoir capacitor and LC filter without a switcher, forming 3.3V.
I think having only SE output is functionally disappointing.
The differential output of OPA1633 seems suitable for adding an XLR output terminal or TPA6120 through a relay.
- 5V to 6V for -5V (VDDL/R) uses TPS61252DSGT.
-In the case of -3.3V, 5V is supplied to the LDO through a 1000uF reservoir capacitor and LC filter without a switcher, forming 3.3V.
I think having only SE output is functionally disappointing.
The differential output of OPA1633 seems suitable for adding an XLR output terminal or TPA6120 through a relay.