Schematics & board layouts etc? Never found that. In the Legacy section?
Edit: Indeed! I hate that; I paid $ 300 for the set years ago
http://www.ap.com/download/splash/250
jan
Edit: Indeed! I hate that; I paid $ 300 for the set years ago
http://www.ap.com/download/splash/250
jan
Last edited:
Hi Bob,
I am one who did your TIM analyzer with a digital meter readout (may I sent at this time some pictures to TAA).
After building my own DAC I had the problem to measure below -100db and then I build my analyzer & generator (also the 3 IM freq.).
The today's used ADC's have a limited bandwidth on the lower corner do the single power voltage and are not fully DC stable.
Yes, may look on my homepage at my latest measurements using a RME BabyFace card. Also the power of today's CPU's using SMP (symmetric multiprocessing) allows to measure in real time. The other drawback is the permanent sound mixer using the MS Windows MME/WDM interface even on digital I/O. ASIO is then the preferred interface or WASAPI.
Some newer IM measurements using an IM cluster in the 15-16k will show up some nice or any other combinations using a "Multi Wave" implementation.
Yes, this the drawback, while the bandwidth & performance is given form the used ADC/DAC. There are still some who bring up higher ADC/DAC performance (Arda Technologies - Home) but currently not seen in any real sound card.
Cheers
Hp
I am one who did your TIM analyzer with a digital meter readout (may I sent at this time some pictures to TAA).
After building my own DAC I had the problem to measure below -100db and then I build my analyzer & generator (also the 3 IM freq.).
The today's used ADC's have a limited bandwidth on the lower corner do the single power voltage and are not fully DC stable.
Yes, may look on my homepage at my latest measurements using a RME BabyFace card. Also the power of today's CPU's using SMP (symmetric multiprocessing) allows to measure in real time. The other drawback is the permanent sound mixer using the MS Windows MME/WDM interface even on digital I/O. ASIO is then the preferred interface or WASAPI.
Some newer IM measurements using an IM cluster in the 15-16k will show up some nice or any other combinations using a "Multi Wave" implementation.
Yes, this the drawback, while the bandwidth & performance is given form the used ADC/DAC. There are still some who bring up higher ADC/DAC performance (Arda Technologies - Home) but currently not seen in any real sound card.
Cheers
Hp
Interestingly, long ago, before I buil my THD analyzer, I used twin T filters tweaked at 1 kHz and 20 kHz to measure amplifier distortion. One thing about the twin T that must be kept in mind is that it still has moderate attenuation an octave away from f0, so seconds in particular will not be read out as high as they really are. However, a common technique is to put feedback around the twin T to reduce attenuation an octave away and sharpen the notch. This, however, can also reduce the depth of the notch, making it more important to optimize the notch. When the twin T is designed carefully, a pot with a small adjustment range in the shunt R leg can be adjusted to optimize the null.
Cheers,
Bob
Hi Samuel,
These are all very good points. Multiplier noise was always a concern of mine and the 5534, while admirably low in noise, can be bettered in the noise department these days. The LM4562, for example has less voltage noise, but at the expense of 4X current noise, implying a desire to operate it in a lower-impedance environment. One should also bear in mind that the tradeoff of noise and agc element distortion (figure of merit, as it were) is also dependent on the amount of agc range one chooses to have. Too little range and the oscillator may run out of agc range at certain frequencies.
I seem to recall I operate the SV in the oscillator at about 1.5V rms, and your point about increasing the operating level to reduce relative noise contribution in the region of f0 is a good one. I do recall being rather conservative about operating level with the worry of increased distortion in the oscillator op amps, but maybe I was too conservative. Perhaps I could have made better tradeoffs back then. An interesting experiment would be for me to increase the operating level by 6 dB and see if the carrier noise about f0 decreases in relative value.
I'm not sure how much better you could do by using 4 separate oscillator to cover each of 4 decades. Note that in my oscillator the agc filtering components are switched to optimum values for each decade range.
Cheers,
Bob
Hi Jan,
If you could send them to me, I'd be grateful.
BTW, Bruce Hofer's AES paper on the SV oscillator for the Tek SG505 was an inspiration for me to get into SVFs for use in both the oscillator and analyzer. I think they also used and SVF for the analyzer in the AA501. They were both still at Tek when I started the design of my THD Analyzer.
Cheers,
Bob
You can download the AP SY1 manual(s) right off AP web site.
AP High Performance Audio Analyzer & Audio Test Instruments : Library
David.
Unless my brief look at the multiplier of your design led me to wrong conclusions the opamp there actually sees just a few hundred Ohms source Z, so one of the nowadays quite common ~1 nV/rtHz opamps (AD797, LT1128, OPA211 etc.) would be a perfect fit.
This would indeed be a rather low level; in the design I implemented I used +14 dBu, and if I'd start all over again I'd probably set it to +20 dBu. Of course this makes opamp and passives distortion more difficult to control, but besides the noise reduction it has other advantages; e.g. it can be shown that the zero in the AGC integrator (which is needed for AGC loop stability) can be set proportionally higher with oscillator level (i.e. R15 in your design could be made smaller). This drastically reduces the effect from level detector ripple.
I've been strictly thinking about a "as good as it gets" design here, not something with a for standard DIY/commercial use realistic cost/complexity.
The multiplier authority (i.e. the Q range it can set the filter to) you mention in your post is a good example where we can optimize a lot by splitting ranges. Typically in the 10-100 kHz range the multiplier authority needs to be an order of magnitude (or even more) higher than at lower frequencies, due to opamp limitations in the integrator stages. Also the track & hold/sample & hold stages are difficult to optimize for a full 4 decade range. A good deal could be done by switching capacitors and resistors, but this quickly gets cumbersome. Altering the multiplier authority for example also affects stability of the AGC loop.
Samuel
@Bob Cordell RE Twin-T filter -- Ken Lewis is using my implementation of an active filter. I borrowed the basic design from John L. Linsley-Hood and used opamps for the active elements. Then I found Rod Elliott's ESP website where he has a nearly identical implementation. I'm using OPA134s currently, but LT1468s might be better.
In any case, with a 1VRMS input, I cannot see any added THD from the active filter -- not saying there isn't any. 2nd H is attenuated less than 0.5dB; 3rd less than 0.2dB; the rest negligible. So the overall result is very good. The filter offers +20dB post-gain to raise very low levels of Harmonics. I use an EMU 0204 for ADC and the ARTA spectrum analyzer for analysis. The combination provides analysis of products out to 90kHz, with the ability to see products well below -130dB. The obvious benefits are low cost and great resolution.
I haven't used twin-tone IM analysis but ARTA does generate the signals. I've mostly been looking at oscillator performance....
In any case, with a 1VRMS input, I cannot see any added THD from the active filter -- not saying there isn't any. 2nd H is attenuated less than 0.5dB; 3rd less than 0.2dB; the rest negligible. So the overall result is very good. The filter offers +20dB post-gain to raise very low levels of Harmonics. I use an EMU 0204 for ADC and the ARTA spectrum analyzer for analysis. The combination provides analysis of products out to 90kHz, with the ability to see products well below -130dB. The obvious benefits are low cost and great resolution.
I haven't used twin-tone IM analysis but ARTA does generate the signals. I've mostly been looking at oscillator performance....
Can somebody tell me how much cordell's oscillator section has THD and THD+N measured with professional equipment as well as measured with PC soundcards.
I am asking because I built cordell's oscillator section only and measured it's distortion with Juli@ balanced inputs. ARTA shown me THD=0.0003% (3ppm) and THD+N=0.0035% (due to free air measurement - no shielding or screening and mains hum). I doubt that Juli@ ADC has 3ppm THD limit because when I connect loop cable from DAC to ADC (balanced) ARTA shows same THD figure 0.0003% (3ppm).
I am asking because I built cordell's oscillator section only and measured it's distortion with Juli@ balanced inputs. ARTA shown me THD=0.0003% (3ppm) and THD+N=0.0035% (due to free air measurement - no shielding or screening and mains hum). I doubt that Juli@ ADC has 3ppm THD limit because when I connect loop cable from DAC to ADC (balanced) ARTA shows same THD figure 0.0003% (3ppm).
The 0.0003% number for the oscillator at 1 kHz when the oscillator is in a metal case sounds about right. Indeed, on a good day, THD+N for the whole analyzer is on the order of 0.0004%. THD without N for the oscillator at 1 kHz should be lower. I've looked at THD without N for the entire analyzer by feeding the residual output to a HP 3580A analog audio spectrum analyzer, but I don't recall what the number was.
I have also learned that the THD of the oscillator depends somewhat strongly on the JFET agc element signal feedback ratio, which theoretically should normally be 50%. For best results, if one can actually measure the real THD of the oscillator, this ratio should be adjustable by a trim pot.
THD of the oscillator at other frequencies may not be as good, but is always below 0.001% from 20Hz to 20kHz.
Cheers,
Bob
Sameer, I think you are essentially seeing the residual of the Juli@, and not the true distortion of the oscillator. My version of Bob's oscillator, which has trim for the AGC JFET, has THD of about half your measurement, but I do use the active Twin-T to reduce the fundamental into the sound card.
Have you seen this from Linear Tech? They claim to have built (not just imagined) a Wien bridge oscillator with parts-per-billion distortion. How many ppb they didn't say because "The measurement of the harmonic distortion of this oscillator defies all of our resources". The Ultrapure Oscillator starts on page 62. The design is based upon the idea that the residual distortion is essentially limited by the amount of feedback available to cancel it out, so they created a "super gain block" to create massively more open-loop gain (180 dB).
This is rather old news, If you read past posts from this thread Jackinnj has some comments on one he built.
Hi Bob/Moore,
Thank you for the answers
On coming Sunday I'll try to measure again with the following configuration. Please tell me Are these points logical ? and also give your suggestions.
1. OPA2134 based active notch filter (Two 9V battery powered).
2. Remove PC from mains line and will run on UPS battery mode to prevent SMPS generated noise slipping into oscillator's transformer which will be powered from mains. (I checked it with FM radio placed in second room PC's SMPS and Mobile phone chargers makes mains line very noisy)
3. Remove additional AGP card from PC which is placed near Juli@ card.
Yes, optimum feedback ratio for JFET varies from device to device even from same batch. Thus, it is good idea to use pot for trimming. In my implementation I used J111 because 2N4091 is not available.
In my personal experience I found that when we run JFET's Vds under 10mV (0.010V) it greatly reduce distortion. So, I think if we can reduce Vds in multiplier section from 60mV to 10mV, this will further enhance distortion figures. What is your opinion ?
Thank you for the answers
On coming Sunday I'll try to measure again with the following configuration. Please tell me Are these points logical ? and also give your suggestions.
1. OPA2134 based active notch filter (Two 9V battery powered).
2. Remove PC from mains line and will run on UPS battery mode to prevent SMPS generated noise slipping into oscillator's transformer which will be powered from mains. (I checked it with FM radio placed in second room PC's SMPS and Mobile phone chargers makes mains line very noisy)
3. Remove additional AGP card from PC which is placed near Juli@ card.
Yes, optimum feedback ratio for JFET varies from device to device even from same batch. Thus, it is good idea to use pot for trimming. In my implementation I used J111 because 2N4091 is not available.
In my personal experience I found that when we run JFET's Vds under 10mV (0.010V) it greatly reduce distortion. So, I think if we can reduce Vds in multiplier section from 60mV to 10mV, this will further enhance distortion figures. What is your opinion ?
someone did a group buy for boards -- i had 4 of my own design burned and some guy from a major semiconductor house bought the other 3! Layout is very critical with the current feedback chips and extremely high gain.
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