My fully discrete ClassD

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Oh, designing the gate-driverstage is the most complicated thing with ClassD...
I think, it's very important to have the correct choice of devices,
these transistors must be able to deliver up to 1 ampere for a short
time, so hfe-curve should not drop to low above ~500ma.
I am not familiar with the 2SC8050...
Cascading more EFs does not really help if the last stage is not able
to deliver the current needed.

Mike
 
2SC8050: 1.5A(max DC current),100MHz
MikeB said:
Oh, designing the gate-driverstage is the most complicated thing with ClassD...
I think, it's very important to have the correct choice of devices,
these transistors must be able to deliver up to 1 ampere for a short
time, so hfe-curve should not drop to low above ~500ma.
I am not familiar with the 2SC8050...
Cascading more EFs does not really help if the last stage is not able
to deliver the current needed.

Mike
 
JohnW: Your work looks really nice!!!!

The 2.2$ was that including the 2 regenerator coils, and bypassing caps? Because in our ZAPpulse we use quite a bit more than 2$ alone for the bypassing caps. 😀

Will the amp get overheated if loaded with 4 Ohms (200W) and will it shut down, or just blow up?

Again i think it's beautiful work! 🙂 Really compact!

Best regards

Lars
 
Sorry to come late to this thread.

I'm looking at the first post schematic, but from skimming through the extensive developments since it appears that there has been no explicit schematic revision to reflect all of the changes---or did I miss something? If not, maybe it's time for a new one (hint hint)?

The one thing that astonished me so far is the scope photo of the gentleman's 2nS risetime P-channel output, showing essentially no ringing! I haven't seen a waveform that clean since I designed some clock drivers for a spectrometer using a self-scanned photodiode array back in ~1978. As it was still the dawn of good power MOSFETs I used RF bipolars in quite an elaborate config., finally steering currents in and out of 100 ohm R's with fast diodes.

I don't know whether (again) I may have missed it, but in my experience it is vital to use a probe with a ground ref springy thing adjacent to the tip, or even better a superfast differential probe like the old Tek product. Otherwise you are looking mostly at the ringing in the scope ground lead.

Anyway, good stuff. As a newbie I am enjoying the forum.
 
Driver Stages

Sorry if I missed anything. You were talking about driver stages. have you considered using a MOSFET driver for the output stage or are we designing completly with BJT's here? I was working on a Class-D amplifier as my honors project for my BE degree last year where I used a IR2113 and I successfully got 60-80Wrms out and I could actually listen to decent audio.
The problem I got was the ringing on the edges (because they were so fast!) was getting back into my small signal stages. This was the sole factor stopping me getting more power outputs.
I would like to spend more time developing it, but now I'm tied up with my masters project designing a Hi-Fi CD pickup. Check out my site for the basics of the design (CB800D).



http://carlslectronics.webhop.net
 
Re: Driver Stages

CarlBenton said:
Sorry if I missed anything. You were talking about driver stages. have you considered using a MOSFET driver for the output stage or are we designing completly with BJT's here?
Umm the thread is called "my fully discrete Class D" 🙂 Presumably it's at least partly a matter of sports.

My own reasons for designing fully discrete circuits are cost, flexibility towards optimisation and (believe it or not)... simplicity. In a half-bridge circuit on a split supply, the extra circuitry needed to interface a comparator living around GND and a FET driver living on the negative rail is about as complicated as and more finicky than both functions executed in 3-legged, 2-junction parts.
 
It looks to me like you're suffering from a awful lot of shoot throught in your design.

The schematic:
An externally hosted image should be here but it was not working when we last tested it.


The simulation
The uppler simulation shows the gate drive voltages. The lower simulation shows the output voltage and the current through the output transistors.
The problem is that the n-mos turns on before the p-mos has turned off. This gives a lot of shoot through when the output svings from high to low. You'll probably get a lot of distortion because of this.
The deadtime when the output swings from low to high, is very long. You should try to minimize this.
An externally hosted image should be here but it was not working when we last tested it.


I've attached the orcad files.
 

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I've worked on the power stage. This (see the schematic) seams to work well. Theres nearly no shoot through, however the switching time might be too long. You can try to minimize R34, R35 together with R21 to target this.

The basic idea behind this gate driver configration, is to connect the two mosfet gates through capasitors, so that they are always in sync. This also decreeses deadtime.
Shoot through is avioded by taking advantage of the gate threshold voltages. You can't turn one mosfet on before the other one is off.

An externally hosted image should be here but it was not working when we last tested it.


Notice that the mosfet currents have been multiplyed with a factor of 10 to make them visible.
An externally hosted image should be here but it was not working when we last tested it.


I've attached the project if any of you would like to work further.

Regards
Kaspar Sinding Meyer
 

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