Measuring deadtime

Dead time can be measured by looking for body diode conduction, which shows up as a blip on the switched node beyond the power rails (either VIN or GND).

When doing the probing, you must eliminate the scope probe ground aligator clip, and attach a straight wire from the scope probe's outer ground shield directly to the ground plane.

The lack of dead time usually manifest itself as smoke, or low efficiency in the best case.

Gate waveform can be misleading. The gate is usually realized using polysilicon, which is resistive, so there's some RC delay between gate pin going low and the channel disappearing. Renesas SO8 FETs are exceptions: the gate resistance is so low, it may kill some drivers. Anyway, the source inductance is probably the limiting factor, unfortunately it is internal to the package, so you can't see the true Vgs.
 
tawen_mei said:
Dead time can be measured by looking for body diode conduction, which shows up as a blip on the switched node beyond the power rails (either VIN or GND).
This means that the dead time is already relatively long. There is absolutely no reason for making the dead time any longer than needed for the coil to force the output to the opposing rail (Iout=0). Making it longer only increases distortion, but does nothing to improve efficiency (worse in fact). Making it shorter improves distortion, but since the charging/discharging of the parasitic capacitance is now partly done through the incoming FET (instead of by the output coil in a resonant transition), idle losses go up. In any case, if you can read dead time from the forward bias "blip", the dead time is too long anyway.

tawen_mei said:
Gate waveform can be misleading. The gate is usually realized using polysilicon, which is resistive, so there's some RC delay between gate pin going low and the channel disappearing. ).
Most power FETs have metal gates. If they were polysilicon they'd be too slow for use in class D. The lead inductances form the limiting factor towards direct readout of the gate waveform. At realistic gate switching speeds (50-100ns), the fidelity of the waveform at the gate pin is still more than sufficient. Faster switching speeds make no sense if the dead time is long enough to be seen as a diode drop on the scope screen.
 

Pierre

Banned
2004-11-26 6:32 am
Paris
Using gate-source waveform to measure deadtime involves setting a "threshold" to distinguis between "on" and "off" state.
Some propose to use the exact moment where gate waveform makes a "glitch" (plateau zone?): that's the moment where the mosfet is really enhanced, right? But when do you say that the mosfet is "off" again?

Another difficulty is to measure both waveforms at a time, as the ground reference is not the same and you can make a shortcircuit with the oscilloscope probe.

If you measure only one Vgs waveform at a time, can you make exact dead-time measurements from that? If not, how is it easily done?

I attach a figure where the plateau zone can be seen (if no one corrects me)
 

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Pierre said:
Using gate-source waveform to measure deadtime involves setting a "threshold" to distinguis between "on" and "off" state.
Some propose to use the exact moment where gate waveform makes a "glitch" (plateau zone?): that's the moment where the mosfet is really enhanced, right? But when do you say that the mosfet is "off" again?
The plateau zone in no way indicates threshold. As long as the FET isn't fully on (=become resistive), Vgs and Id are directly related per the transfer function.
Pierre said:
Another difficulty is to measure both waveforms at a time, as the ground reference is not the same and you can make a shortcircuit with the oscilloscope probe.
You can read everything from only one gate waveform. For practical reasons you would take the bottom FET. Of course you'll want to check the high side behaves similarly. This is done using the oscilloscope's A-B mode. You would never want to tie the scope chassis to a switching waveform.
Pierre said:
I attach a figure where the plateau zone can be seen (if no one corrects me)
It looks like it.
 

Pierre

Banned
2004-11-26 6:32 am
Paris
Then, looking at the low side Vgs waveform, in order to measure dead-time with some precision, where exactly do you take the ON state and the OFF state? That's my main question.
Depending on that you will have a deadtime or another. Do you assign the "on" state as soon as it reaches the nominal threshold from the datasheet and "off" when it crosses it again?

I assume that this measurement are done with no signal and the output loaded with the nominal load (although that shouldn't change things too much, imho).
 
Pierre said:
Do you assign the "on" state as soon as it reaches the nominal threshold from the datasheet and "off" when it crosses it again?

A FET is "on" when it is has become a resistor. A FET is "off" when no drain current flows while Vds>>0. The bit in-between is where the action is, and this cannot be treated using a simple variable called "dead time".
 

Pierre

Banned
2004-11-26 6:32 am
Paris
OK, Bruno, but you stated that you must measure dead-time by looking at the gate waveform.
Then you must see something that tells you that the mosfet is "on" (of course, when it is behaving like a resistor). The question is: do you consider that this point is reached at threshold voltage or do you look at some other characteristic in the Vgs waveform to determine when the mosfet is conducting?
 
phase_accurate said:
What do you think about making the dead-time variable and setting it for minimum idle current ?
The 400W modules have a pot to set idle current. Setting idle current to minimum (around 35mA) results in a ridiculous amount of distortion. Setting it at 60mA produces good THD performance. The increase in idle losses corresponds to the energy in snubbers and parasitics that is not recovered by the inductor, so still no cross-conduction. The increased idle losses are a small premium for the better performance.
 
phase_accurate said:
So you would recommend to start at minimum idle-current and then decrease dead-time until THD is smallest ?
I wouldn't recommend doing anything with this potentiometer. It's set at the factory for 60 to 70mA.

phase_accurate said:
What about ageing and thermal runaway ?
Aging is not a significant factor. Temperature coefficients across the circuit are matched.
 
phase_accurate said:
Sorry for being unspecific.
I wondered how to optimally set dead-time in general - not on an industrially manufactured module - since there are some people developing their own class-d amps .....
My only problem is - Feind hört mit. I could tell you all the details in private, but not in a forum which is ostensibly visited by prospective competitors. The basic answer is: for low THD, as short as possible without causing shoot-through. For low idle current: precisely as long as the resonant transition.
 
Telling this in private can be dangerous as well since you'l never know what job someone is going to apply for some day !

I just wanted to know what (simple) procedure you would suggest if someone uses adjustable deadtime on an amp (which is quite eays to implement) to set said deadtime.

On an amp I once made we just set it for lowest idle current which was not the best choice obviously. Since I don't own this one anymore I can't play around with it now. But I assume we'd have achieved better THD with the same circuit by optimising deadtime than we actually did.

Regards

Charles
 
Hi,

If the mosfet could be considered ON when the plateau region is over (gate voltage now climbing sharply again) could it not be considered OFF at the beginning of the plateau region?

I realise some current may and likely is flowing at this point, and how much is likely to vary, but there's still full voltage across the device...

I'd think that's actually the point you'd be concerned with, when the voltage starts dropping across it (the start of the plateau region), is when your output node actually switches, and so would be at the end of deadtime.

I'd noticed before that instantaneous output current can shift the plateau region as well, some data sheets show this directly in the gate charge waveforms.

We aren't talking about any particular designs here just good techniques so nothing should be top secret? Of course I see things differently from my end of things.

I still think temperature is a prime indicator if you're on the right track or not, not everyone has the 100Ghz scopes.
Regards,
Chris
 
classd4sure said:
If the mosfet could be considered ON when the plateau region is over (gate voltage now climbing sharply again) could it not be considered OFF at the beginning of the plateau region?
NO! The drain voltage may not have started coming down yet, but the FET is already conducting. It may only be considered OFF when Vgs<Vth.
classd4sure said:
I realise some current may and likely is flowing at this point, and how much is likely to vary, but there's still full voltage across the device...
Precisely. If the output stage is delivering, say 10A and you're on the "hard" transition, plateau starts only at Id=10A. This is not quite what you'd call "off".
classd4sure said:
I'd think that's actually the point you'd be concerned with, when the voltage starts dropping across it (the start of the plateau region), is when your output node actually switches, and so would be at the end of deadtime.
Hmmmm... I've often dreamt about making an adaptive control circuit that made for negative dead time so it always crosses over precisely at Id=Iout. Hugely interesting, both in terms of distortion and efficiency, but "fairly" impractical.
classd4sure said:
I'd noticed before that instantaneous output current can shift the plateau region as well, some data sheets show this directly in the gate charge waveforms.
This is quite obvious. As long as the FET is transitioning (Vds is moving down), the miller effect will insure that Vgs cannot move beyond the point corresponding with drain current.
It's quite simple, isn't it? If Vds>>0, Id is determined only by Vgs. If Vgs were higher, either Vds should be 0 or there should be shoot-through preventing Vds from coming down.
classd4sure said:
We aren't talking about any particular designs here just good techniques so nothing should be top secret? Of course I see things differently from my end of things.
As I explained in private earlier, I try to point people in the right direction, without giving recipes. Recipes do not constitute "understanding". Understanding comes only through study, experimentation, and at times a friendly hint from others.
There are too many people around who try to cream recipes from forums such as these in order to get into the market with their "own" designs quickly, without feeling the need to understand what they're doing. I don't feel any need to give these people a cheap ride by writing a "how-to" guide.

However, there are a few folks out here who themselves work and study hard to gain a proper in-depth understanding. There, it makes little sense to withold information. You yourself, for instance, will find out these things in due time anyway. So then I think it's worth to give nudges in the right direction, knowing full well that these hints won't be understood by people simply looking for a quick design help.