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How close do the MOS-FETs in an Aleph 4 have to be?
I bought a batch of 24 and have ascertained that they are all within 3% of each other.
Biassed at approximately 5V, I measured Vgs and Is at exactly 39.4 Degrees C. Is was typically set at 400mA +/- 5%.
As Vgs differred over the test range by 0.3V I normalised the figures assuming that the MOS-FETs were behaving in a linear fashion. i.e. I did a bit of maths to work out what Is should have been id Vgs was constant throughout the test.
Bearing in mind that the MOS-FETs are from a single production run, I expected them to be closely matched anyway.
The normalised figures give me a spread of Vgs = 5.14V to 4.88V to maintain an Is of 450mA.
If I further divide the group into batches of 6 MOS-FETs, the Vgs figures are well within 0.1V of each other.
The next task will be to group the MOS-FETs onto their x 6 PCBs and give them a regulated Vgs to check if they are sharing the current as expected.
Hi Andy,
your range of 4.88Vgs to 5.14Vgs is enormous.
Matched at a fixed Is is usually done to better than 50mV and some match to better than 10mVgs.
If you have 100mVgs range for each of your groups then check the groups again.
Select a REF from the middle of the first group to be checked.
Set up a jig to hold the two mosFETs in Thermal contact, possibly with a thin sheet of copper or aluminium between, if some cooling is needed. The second FET is the DUT. You will compare all the DUTs to the REF (for that group).
Connect the two sources together at the jig.
Connect the two gates together at the jig.
Connect a 10r resistor from each jig Drain pin to your power source. This allows measurement of your drain currents.
Arrange a variable Vgs using a pot between +ve and -ve to feed the common gate pin with voltage.
Turn up Vgs while monitoring the 10r Vdrop. Increase till you reach operating quiescent current. Now measure the difference between the two drain currents.
Check to see the spread in drain currents for each group.
If the Id are within 10% in any group then OK.
If the spread approaches or exceeds 20% then you will find parallel pairs in the amp will not pass equal currents. This results in some devices running hotter.
This increases the stress they will have while operating.
your range of 4.88Vgs to 5.14Vgs is enormous.
Matched at a fixed Is is usually done to better than 50mV and some match to better than 10mVgs.
If you have 100mVgs range for each of your groups then check the groups again.
Select a REF from the middle of the first group to be checked.
Set up a jig to hold the two mosFETs in Thermal contact, possibly with a thin sheet of copper or aluminium between, if some cooling is needed. The second FET is the DUT. You will compare all the DUTs to the REF (for that group).
Connect the two sources together at the jig.
Connect the two gates together at the jig.
Connect a 10r resistor from each jig Drain pin to your power source. This allows measurement of your drain currents.
Arrange a variable Vgs using a pot between +ve and -ve to feed the common gate pin with voltage.
Turn up Vgs while monitoring the 10r Vdrop. Increase till you reach operating quiescent current. Now measure the difference between the two drain currents.
Check to see the spread in drain currents for each group.
If the Id are within 10% in any group then OK.
If the spread approaches or exceeds 20% then you will find parallel pairs in the amp will not pass equal currents. This results in some devices running hotter.
This increases the stress they will have while operating.
I've got 75 MOS-FETs in total. I intended to roughly match them as above and then fit them in groups of 6 on the PCBs to see how they behaved together. Only when they are thermally coupled together and all the devices are connected as a group can I apply a reference Vgs and measure each devices share of the load current. Hopefully this will show them in their operating environment. If each device is supposed to be running at 400mA, how close does the matching have to be ??
did you say you remeasured with the 1r5 source resistor in the test circuit?
A source resistor in the test circuit acts like feedback and compensates for Vgs differences. The 600mVrs will completely swamp the 1mV to 50mV variations in the device Vgs.
I think you should match with Rs=0r0 or <=0r1 and then use the incircuit Rs value to bring the operating currents closer to each other. Rs is particularly useful as output current increases towards peak value. It becomes the main voltage drop in the Vgs+Vrs and thus holds the devices in current balance.
A source resistor in the test circuit acts like feedback and compensates for Vgs differences. The 600mVrs will completely swamp the 1mV to 50mV variations in the device Vgs.
I think you should match with Rs=0r0 or <=0r1 and then use the incircuit Rs value to bring the operating currents closer to each other. Rs is particularly useful as output current increases towards peak value. It becomes the main voltage drop in the Vgs+Vrs and thus holds the devices in current balance.
Andy,
that 390mA across the 34r drops ~10V. That leaves ~7Vds on the DUT.
The DUT is consuming ~1.5W. The junction is heating quite rapidly even though the outside case temperature has hardly changed.
It will be very difficult to get consistent absolute results measuring single DUTs this way.
Vgs/Id is very dependent on Tj. How can you hold Tj constant?
That is why I recommend REF + DUT and use comparison for matching.
that 390mA across the 34r drops ~10V. That leaves ~7Vds on the DUT.
The DUT is consuming ~1.5W. The junction is heating quite rapidly even though the outside case temperature has hardly changed.
It will be very difficult to get consistent absolute results measuring single DUTs this way.
Vgs/Id is very dependent on Tj. How can you hold Tj constant?
That is why I recommend REF + DUT and use comparison for matching.
This is how I matched IRFP240s measuring Vgs at 1A for :
At drain and gate I used resistor 1R0 connected to regulated power supply adjusted to about 5.4V to have about 1V drop on the resistor. The transistor was mounted at large heatsink w/o thermal paste. I measured the voltage drop not at gate/source of transistor (about 4.4V) but at the resistor (about 1V). It allowed me to use lowest voltage range at my tester with maximum accuracy. After that I was changing transistors keeping the same voltage at the regulated power supply and measuring the drops across the resistor.
At drain and gate I used resistor 1R0 connected to regulated power supply adjusted to about 5.4V to have about 1V drop on the resistor. The transistor was mounted at large heatsink w/o thermal paste. I measured the voltage drop not at gate/source of transistor (about 4.4V) but at the resistor (about 1V). It allowed me to use lowest voltage range at my tester with maximum accuracy. After that I was changing transistors keeping the same voltage at the regulated power supply and measuring the drops across the resistor.
Andrew,
I have just verified my matching by your method with the first group of 6 x MOSFETs. During testing I have held them at a constant temperature (as best as possible). My initial results were all within 10-20mV Vgs of each other, with your suggested measuring, they are all within 1% of each other.
I have just verified my matching by your method with the first group of 6 x MOSFETs. During testing I have held them at a constant temperature (as best as possible). My initial results were all within 10-20mV Vgs of each other, with your suggested measuring, they are all within 1% of each other.
1% Id match at equal Vgs is incredible.
I don't think I have explained the DUT/REF method correctly.
Are you able post some pictures? I have always test mosfets individually. Wrong?
Going through all the MOS-FETs I am getting completely different results which each method I'm using.
OK. Tj is important, I'm trying my utmost to bolt each DUT onto a huge heatsink which is temperature controlled. Each test is started at 25 Deg C and measurements are taken at 400mA and 40 Deg C. Using this method I can get the Vgs figures within groups of 6 to +/- 20mV. Please bear in mind that all my MOS-FETs are from a single production batch.
Using Andrew T's method it is tricky to stabilize Is sufficiently to take accurate readings. But reading each DVM across the 10R Drain Resistors, they are within 0.01V of each other - NOT IN ALL CASES.
Why does Nelson suggest his method of testing them if everyone else is poo-pooing that method ?
OK. Tj is important, I'm trying my utmost to bolt each DUT onto a huge heatsink which is temperature controlled. Each test is started at 25 Deg C and measurements are taken at 400mA and 40 Deg C. Using this method I can get the Vgs figures within groups of 6 to +/- 20mV. Please bear in mind that all my MOS-FETs are from a single production batch.
Using Andrew T's method it is tricky to stabilize Is sufficiently to take accurate readings. But reading each DVM across the 10R Drain Resistors, they are within 0.01V of each other - NOT IN ALL CASES.
Why does Nelson suggest his method of testing them if everyone else is poo-pooing that method ?
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Here's the basic set-up.
The REF MOS-FET is on the LEFT in close thermal contact with the other 5 of it's group.
Two DVMs are used to measure Is across the 2 x 10R resistors. The whole lot is powered by a bench test PSU at 17V and Vgs can be varied with the pot.
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