LT3042/3045 LTSpice simulation

At about half way down the product pages under Ltspice simulations are files for 3.8-20V to 3.3V @ 500mA and 3.8-20V to 3.3V @ 200mA.

Here are the links:

https://www.analog.com/media/en/simulation-models/LTspice-demo-circuits/LT3045_DC2491A.asc

https://www.analog.com/media/en/simulation-models/LTspice-demo-circuits/LT3042_DC2246A.asc

You can also find lt3042 and lt3045 demonstration files that you can play with (named 3042.asc and 3045.asc) hidden away in this ltspice windows directory:

"C:\Users\username\Documents\LTspiceXVII\examples\jigs"
 
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You have B and C shorted on your sim, also you have Vin set at just 5.5 volts. This is a linear reg and so needs at least 18v plus some headroom... which is getting toward maximum ratings for the chip. The voltage setting resistor needs altering to around 221k.

Its not an ideal application for this chip imo (your 18 volts requirement), in fact the data sheet specifies 15 volts as a maximum regulated output.
 
The inner CCS push 0.1mA current to SET pin, so there 150k represents 15V output.
 

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> Would this PSRR curve be correct

-196dB is not creditable in a real-world circuit. It "might" happen through lucky cancellation, but don't bet on it. Or expect to real-life measure (or hear!) it.

>100dB is creditable, in a simulation, although real life parasitics will spoil this.
 
Thanks.

I can't seem to run PSRR and impedance simulations.

Do you know how to set things up for it to run?

PSRR: run "AC Analysis" with 1V AC input. The result is the output.

Output impedance:
Delete input AC amplitude.
Run "AC Analysis" with 1V AC in current source (Advanced-AC amplitude=1) -as load-.
Plot output voltage. Plot current source current.
Retype V(v+) to V(v+)/I(I1).
Set left vertical axis to linear.
 

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  • Diyinhk 15V output impedance 2.jpg
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  • Diyinhk 15V output impedance.jpg
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  • DIYINHK_15V.asc
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OK, could run the impedance simulation.

Why does it take so long to run? Is there something that could be done for it to run faster?

In other power supply simulations I am doing now the run time is just a few seconds, almost instantly. Why here is different?

Can you feed a negative voltage to have negative output regulator?
 
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These curves are based on simulations I did, with regulators based on the datasheet.

So the schematics have some more parts than those that are used by DIYINHK.

Perhaps someone can explain me why the differences or the parts missing from the DIYINHK design.

As I didn't quite like the ascending PSRR curve, I am now simulating that adding a CRC filter at the input, with remarkable results.
 

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When doing these simulations, the first electrolytic capacitor (connected to the voltage source) is useless except if you define some series resistance of this voltage source, just try 🙂.
Of course in the real life the things are different...
 
These curves are based on simulations I did, with regulators based on the datasheet.

So the schematics have some more parts than those that are used by DIYINHK.

Perhaps someone can explain me why the differences or the parts missing from the DIYINHK design.

As I didn't quite like the ascending PSRR curve, I am now simulating that adding a CRC filter at the input, with remarkable results.


BTW, I do not see any kind of load on the first picture?